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<title>DM-CtrlH7-BF-DevProgram: C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h Source File</title>
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<div class="header">
  <div class="headertitle"><div class="title">stm32h7xx_ll_tim.h</div></div>
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<a href="stm32h7xx__ll__tim_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span></div>
<div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span> </div>
<div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">/* Define to prevent recursive inclusion -------------------------------------*/</span></div>
<div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="preprocessor">#ifndef __STM32H7xx_LL_TIM_H</span></div>
<div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="preprocessor">#define __STM32H7xx_LL_TIM_H</span></div>
<div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span> </div>
<div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div>
<div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span><span class="preprocessor">#endif</span></div>
<div class="line"><a id="l00026" name="l00026"></a><span class="lineno">   26</span> </div>
<div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span><span class="comment">/* Includes ------------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span><span class="preprocessor">#include &quot;<a class="code" href="stm32h7xx_8h.html">stm32h7xx.h</a>&quot;</span></div>
<div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span></div>
<div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span> </div>
<div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span><span class="preprocessor">#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)</span></div>
<div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span></div>
<div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span> </div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span><span class="comment">/* Private types -------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span><span class="comment">/* Private variables ---------------------------------------------------------*/</span></div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span><span class="keyword">static</span> <span class="keyword">const</span> uint8_t OFFSET_TAB_CCMRx[] =</div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>{</div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>  0x00U,   <span class="comment">/* 0: TIMx_CH1  */</span></div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>  0x00U,   <span class="comment">/* 1: TIMx_CH1N */</span></div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>  0x00U,   <span class="comment">/* 2: TIMx_CH2  */</span></div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>  0x00U,   <span class="comment">/* 3: TIMx_CH2N */</span></div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>  0x04U,   <span class="comment">/* 4: TIMx_CH3  */</span></div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>  0x04U,   <span class="comment">/* 5: TIMx_CH3N */</span></div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>  0x04U,   <span class="comment">/* 6: TIMx_CH4  */</span></div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>  0x3CU,   <span class="comment">/* 7: TIMx_CH5  */</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>  0x3CU    <span class="comment">/* 8: TIMx_CH6  */</span></div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>};</div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span> </div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span><span class="keyword">static</span> <span class="keyword">const</span> uint8_t SHIFT_TAB_OCxx[] =</div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>{</div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>  0U,            <span class="comment">/* 0: OC1M, OC1FE, OC1PE */</span></div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>  0U,            <span class="comment">/* 1: - NA */</span></div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>  8U,            <span class="comment">/* 2: OC2M, OC2FE, OC2PE */</span></div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>  0U,            <span class="comment">/* 3: - NA */</span></div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>  0U,            <span class="comment">/* 4: OC3M, OC3FE, OC3PE */</span></div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>  0U,            <span class="comment">/* 5: - NA */</span></div>
<div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>  8U,            <span class="comment">/* 6: OC4M, OC4FE, OC4PE */</span></div>
<div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>  0U,            <span class="comment">/* 7: OC5M, OC5FE, OC5PE */</span></div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>  8U             <span class="comment">/* 8: OC6M, OC6FE, OC6PE */</span></div>
<div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>};</div>
<div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span> </div>
<div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span><span class="keyword">static</span> <span class="keyword">const</span> uint8_t SHIFT_TAB_ICxx[] =</div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>{</div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>  0U,            <span class="comment">/* 0: CC1S, IC1PSC, IC1F */</span></div>
<div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>  0U,            <span class="comment">/* 1: - NA */</span></div>
<div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>  8U,            <span class="comment">/* 2: CC2S, IC2PSC, IC2F */</span></div>
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>  0U,            <span class="comment">/* 3: - NA */</span></div>
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>  0U,            <span class="comment">/* 4: CC3S, IC3PSC, IC3F */</span></div>
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>  0U,            <span class="comment">/* 5: - NA */</span></div>
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>  8U,            <span class="comment">/* 6: CC4S, IC4PSC, IC4F */</span></div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>  0U,            <span class="comment">/* 7: - NA */</span></div>
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>  0U             <span class="comment">/* 8: - NA */</span></div>
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>};</div>
<div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span> </div>
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span><span class="keyword">static</span> <span class="keyword">const</span> uint8_t SHIFT_TAB_CCxP[] =</div>
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>{</div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>  0U,            <span class="comment">/* 0: CC1P */</span></div>
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>  2U,            <span class="comment">/* 1: CC1NP */</span></div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>  4U,            <span class="comment">/* 2: CC2P */</span></div>
<div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>  6U,            <span class="comment">/* 3: CC2NP */</span></div>
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>  8U,            <span class="comment">/* 4: CC3P */</span></div>
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>  10U,           <span class="comment">/* 5: CC3NP */</span></div>
<div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>  12U,           <span class="comment">/* 6: CC4P */</span></div>
<div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>  16U,           <span class="comment">/* 7: CC5P */</span></div>
<div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>  20U            <span class="comment">/* 8: CC6P */</span></div>
<div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>};</div>
<div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span> </div>
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span><span class="keyword">static</span> <span class="keyword">const</span> uint8_t SHIFT_TAB_OISx[] =</div>
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>{</div>
<div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>  0U,            <span class="comment">/* 0: OIS1 */</span></div>
<div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>  1U,            <span class="comment">/* 1: OIS1N */</span></div>
<div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>  2U,            <span class="comment">/* 2: OIS2 */</span></div>
<div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>  3U,            <span class="comment">/* 3: OIS2N */</span></div>
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>  4U,            <span class="comment">/* 4: OIS3 */</span></div>
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>  5U,            <span class="comment">/* 5: OIS3N */</span></div>
<div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>  6U,            <span class="comment">/* 6: OIS4 */</span></div>
<div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>  8U,            <span class="comment">/* 7: OIS5 */</span></div>
<div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>  10U            <span class="comment">/* 8: OIS6 */</span></div>
<div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>};</div>
<div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span> </div>
<div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span><span class="comment">/* Private constants ---------------------------------------------------------*/</span></div>
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span> </div>
<div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span><span class="preprocessor">#if   defined(TIM_BREAK_INPUT_SUPPORT)</span></div>
<div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span><span class="comment">/* Defines used for the bit position in the register and perform offsets */</span></div>
<div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span><span class="preprocessor">#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) &amp; 0x1FUL)</span></div>
<div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span> </div>
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span><span class="comment">/* Generic bit definitions for TIMx_AF1 register */</span></div>
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span><span class="preprocessor">#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span><span class="preprocessor">#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span><span class="preprocessor">#endif </span><span class="comment">/* TIM_BREAK_INPUT_SUPPORT */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span> </div>
<div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span> </div>
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span><span class="comment">/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */</span></div>
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span><span class="preprocessor">#define DT_DELAY_1 ((uint8_t)0x7F)</span></div>
<div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span><span class="preprocessor">#define DT_DELAY_2 ((uint8_t)0x3F)</span></div>
<div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span><span class="preprocessor">#define DT_DELAY_3 ((uint8_t)0x1F)</span></div>
<div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span><span class="preprocessor">#define DT_DELAY_4 ((uint8_t)0x1F)</span></div>
<div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span> </div>
<div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span><span class="comment">/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */</span></div>
<div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span><span class="preprocessor">#define DT_RANGE_1 ((uint8_t)0x00)</span></div>
<div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span><span class="preprocessor">#define DT_RANGE_2 ((uint8_t)0x80)</span></div>
<div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span><span class="preprocessor">#define DT_RANGE_3 ((uint8_t)0xC0)</span></div>
<div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span><span class="preprocessor">#define DT_RANGE_4 ((uint8_t)0xE0)</span></div>
<div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span> </div>
<div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span></div>
<div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span> </div>
<div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span><span class="comment">/* Private macros ------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span><span class="preprocessor">#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \</span></div>
<div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span><span class="preprocessor">  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\</span></div>
<div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span><span class="preprocessor">   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\</span></div>
<div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span><span class="preprocessor">   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\</span></div>
<div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span><span class="preprocessor">   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\</span></div>
<div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span><span class="preprocessor">   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\</span></div>
<div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span><span class="preprocessor">   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\</span></div>
<div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span><span class="preprocessor">   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\</span></div>
<div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span><span class="preprocessor">   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)</span></div>
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span></div>
<div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span><span class="preprocessor">#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \</span></div>
<div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span><span class="preprocessor">  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \</span></div>
<div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span><span class="preprocessor">   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) &gt;&gt; 1U)) : \</span></div>
<div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span><span class="preprocessor">   ((uint64_t)1000000000000U/((__TIMCLK__) &gt;&gt; 2U)))</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span> </div>
<div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span> </div>
<div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span><span class="comment">/* Exported types ------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span><span class="preprocessor">#if defined(USE_FULL_LL_DRIVER)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span></div>
<div class="line"><a id="l00198" name="l00198"></a><span class="lineno">  198</span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a id="l00199" name="l00199"></a><span class="lineno">  199</span>{</div>
<div class="line"><a id="l00200" name="l00200"></a><span class="lineno">  200</span>  uint16_t Prescaler;         </div>
<div class="line"><a id="l00205" name="l00205"></a><span class="lineno">  205</span> </div>
<div class="line"><a id="l00206" name="l00206"></a><span class="lineno">  206</span>  uint32_t CounterMode;       </div>
<div class="line"><a id="l00211" name="l00211"></a><span class="lineno">  211</span> </div>
<div class="line"><a id="l00212" name="l00212"></a><span class="lineno">  212</span>  uint32_t Autoreload;        </div>
<div class="line"><a id="l00220" name="l00220"></a><span class="lineno">  220</span> </div>
<div class="line"><a id="l00221" name="l00221"></a><span class="lineno">  221</span>  uint32_t ClockDivision;     </div>
<div class="line"><a id="l00226" name="l00226"></a><span class="lineno">  226</span> </div>
<div class="line"><a id="l00227" name="l00227"></a><span class="lineno">  227</span>  uint32_t RepetitionCounter;  </div>
<div class="line"><a id="l00240" name="l00240"></a><span class="lineno">  240</span>} LL_TIM_InitTypeDef;</div>
<div class="line"><a id="l00241" name="l00241"></a><span class="lineno">  241</span></div>
<div class="line"><a id="l00245" name="l00245"></a><span class="lineno">  245</span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a id="l00246" name="l00246"></a><span class="lineno">  246</span>{</div>
<div class="line"><a id="l00247" name="l00247"></a><span class="lineno">  247</span>  uint32_t OCMode;        </div>
<div class="line"><a id="l00252" name="l00252"></a><span class="lineno">  252</span> </div>
<div class="line"><a id="l00253" name="l00253"></a><span class="lineno">  253</span>  uint32_t OCState;       </div>
<div class="line"><a id="l00258" name="l00258"></a><span class="lineno">  258</span> </div>
<div class="line"><a id="l00259" name="l00259"></a><span class="lineno">  259</span>  uint32_t OCNState;      </div>
<div class="line"><a id="l00264" name="l00264"></a><span class="lineno">  264</span> </div>
<div class="line"><a id="l00265" name="l00265"></a><span class="lineno">  265</span>  uint32_t CompareValue;  </div>
<div class="line"><a id="l00270" name="l00270"></a><span class="lineno">  270</span> </div>
<div class="line"><a id="l00271" name="l00271"></a><span class="lineno">  271</span>  uint32_t OCPolarity;    </div>
<div class="line"><a id="l00276" name="l00276"></a><span class="lineno">  276</span> </div>
<div class="line"><a id="l00277" name="l00277"></a><span class="lineno">  277</span>  uint32_t OCNPolarity;   </div>
<div class="line"><a id="l00282" name="l00282"></a><span class="lineno">  282</span> </div>
<div class="line"><a id="l00283" name="l00283"></a><span class="lineno">  283</span> </div>
<div class="line"><a id="l00284" name="l00284"></a><span class="lineno">  284</span>  uint32_t OCIdleState;   </div>
<div class="line"><a id="l00289" name="l00289"></a><span class="lineno">  289</span> </div>
<div class="line"><a id="l00290" name="l00290"></a><span class="lineno">  290</span>  uint32_t OCNIdleState;  </div>
<div class="line"><a id="l00295" name="l00295"></a><span class="lineno">  295</span>} LL_TIM_OC_InitTypeDef;</div>
<div class="line"><a id="l00296" name="l00296"></a><span class="lineno">  296</span></div>
<div class="line"><a id="l00300" name="l00300"></a><span class="lineno">  300</span> </div>
<div class="line"><a id="l00301" name="l00301"></a><span class="lineno">  301</span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a id="l00302" name="l00302"></a><span class="lineno">  302</span>{</div>
<div class="line"><a id="l00303" name="l00303"></a><span class="lineno">  303</span> </div>
<div class="line"><a id="l00304" name="l00304"></a><span class="lineno">  304</span>  uint32_t ICPolarity;    </div>
<div class="line"><a id="l00309" name="l00309"></a><span class="lineno">  309</span> </div>
<div class="line"><a id="l00310" name="l00310"></a><span class="lineno">  310</span>  uint32_t ICActiveInput; </div>
<div class="line"><a id="l00315" name="l00315"></a><span class="lineno">  315</span> </div>
<div class="line"><a id="l00316" name="l00316"></a><span class="lineno">  316</span>  uint32_t ICPrescaler;   </div>
<div class="line"><a id="l00321" name="l00321"></a><span class="lineno">  321</span> </div>
<div class="line"><a id="l00322" name="l00322"></a><span class="lineno">  322</span>  uint32_t ICFilter;      </div>
<div class="line"><a id="l00327" name="l00327"></a><span class="lineno">  327</span>} LL_TIM_IC_InitTypeDef;</div>
<div class="line"><a id="l00328" name="l00328"></a><span class="lineno">  328</span> </div>
<div class="line"><a id="l00329" name="l00329"></a><span class="lineno">  329</span></div>
<div class="line"><a id="l00333" name="l00333"></a><span class="lineno">  333</span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a id="l00334" name="l00334"></a><span class="lineno">  334</span>{</div>
<div class="line"><a id="l00335" name="l00335"></a><span class="lineno">  335</span>  uint32_t EncoderMode;     </div>
<div class="line"><a id="l00340" name="l00340"></a><span class="lineno">  340</span> </div>
<div class="line"><a id="l00341" name="l00341"></a><span class="lineno">  341</span>  uint32_t IC1Polarity;     </div>
<div class="line"><a id="l00346" name="l00346"></a><span class="lineno">  346</span> </div>
<div class="line"><a id="l00347" name="l00347"></a><span class="lineno">  347</span>  uint32_t IC1ActiveInput;  </div>
<div class="line"><a id="l00352" name="l00352"></a><span class="lineno">  352</span> </div>
<div class="line"><a id="l00353" name="l00353"></a><span class="lineno">  353</span>  uint32_t IC1Prescaler;    </div>
<div class="line"><a id="l00358" name="l00358"></a><span class="lineno">  358</span> </div>
<div class="line"><a id="l00359" name="l00359"></a><span class="lineno">  359</span>  uint32_t IC1Filter;       </div>
<div class="line"><a id="l00364" name="l00364"></a><span class="lineno">  364</span> </div>
<div class="line"><a id="l00365" name="l00365"></a><span class="lineno">  365</span>  uint32_t IC2Polarity;      </div>
<div class="line"><a id="l00370" name="l00370"></a><span class="lineno">  370</span> </div>
<div class="line"><a id="l00371" name="l00371"></a><span class="lineno">  371</span>  uint32_t IC2ActiveInput;  </div>
<div class="line"><a id="l00376" name="l00376"></a><span class="lineno">  376</span> </div>
<div class="line"><a id="l00377" name="l00377"></a><span class="lineno">  377</span>  uint32_t IC2Prescaler;    </div>
<div class="line"><a id="l00382" name="l00382"></a><span class="lineno">  382</span> </div>
<div class="line"><a id="l00383" name="l00383"></a><span class="lineno">  383</span>  uint32_t IC2Filter;       </div>
<div class="line"><a id="l00388" name="l00388"></a><span class="lineno">  388</span> </div>
<div class="line"><a id="l00389" name="l00389"></a><span class="lineno">  389</span>} LL_TIM_ENCODER_InitTypeDef;</div>
<div class="line"><a id="l00390" name="l00390"></a><span class="lineno">  390</span></div>
<div class="line"><a id="l00394" name="l00394"></a><span class="lineno">  394</span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a id="l00395" name="l00395"></a><span class="lineno">  395</span>{</div>
<div class="line"><a id="l00396" name="l00396"></a><span class="lineno">  396</span> </div>
<div class="line"><a id="l00397" name="l00397"></a><span class="lineno">  397</span>  uint32_t IC1Polarity;        </div>
<div class="line"><a id="l00402" name="l00402"></a><span class="lineno">  402</span> </div>
<div class="line"><a id="l00403" name="l00403"></a><span class="lineno">  403</span>  uint32_t IC1Prescaler;       </div>
<div class="line"><a id="l00410" name="l00410"></a><span class="lineno">  410</span> </div>
<div class="line"><a id="l00411" name="l00411"></a><span class="lineno">  411</span>  uint32_t IC1Filter;          </div>
<div class="line"><a id="l00417" name="l00417"></a><span class="lineno">  417</span> </div>
<div class="line"><a id="l00418" name="l00418"></a><span class="lineno">  418</span>  uint32_t CommutationDelay;   </div>
<div class="line"><a id="l00425" name="l00425"></a><span class="lineno">  425</span>} LL_TIM_HALLSENSOR_InitTypeDef;</div>
<div class="line"><a id="l00426" name="l00426"></a><span class="lineno">  426</span></div>
<div class="line"><a id="l00430" name="l00430"></a><span class="lineno">  430</span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a id="l00431" name="l00431"></a><span class="lineno">  431</span>{</div>
<div class="line"><a id="l00432" name="l00432"></a><span class="lineno">  432</span>  uint32_t OSSRState;            </div>
<div class="line"><a id="l00440" name="l00440"></a><span class="lineno">  440</span> </div>
<div class="line"><a id="l00441" name="l00441"></a><span class="lineno">  441</span>  uint32_t OSSIState;            </div>
<div class="line"><a id="l00449" name="l00449"></a><span class="lineno">  449</span> </div>
<div class="line"><a id="l00450" name="l00450"></a><span class="lineno">  450</span>  uint32_t LockLevel;            </div>
<div class="line"><a id="l00455" name="l00455"></a><span class="lineno">  455</span> </div>
<div class="line"><a id="l00456" name="l00456"></a><span class="lineno">  456</span>  uint8_t DeadTime;              </div>
<div class="line"><a id="l00465" name="l00465"></a><span class="lineno">  465</span> </div>
<div class="line"><a id="l00466" name="l00466"></a><span class="lineno">  466</span>  uint16_t BreakState;           </div>
<div class="line"><a id="l00474" name="l00474"></a><span class="lineno">  474</span> </div>
<div class="line"><a id="l00475" name="l00475"></a><span class="lineno">  475</span>  uint32_t BreakPolarity;        </div>
<div class="line"><a id="l00483" name="l00483"></a><span class="lineno">  483</span> </div>
<div class="line"><a id="l00484" name="l00484"></a><span class="lineno">  484</span>  uint32_t BreakFilter;          </div>
<div class="line"><a id="l00492" name="l00492"></a><span class="lineno">  492</span> </div>
<div class="line"><a id="l00493" name="l00493"></a><span class="lineno">  493</span><span class="preprocessor">#if defined(TIM_BDTR_BKBID)</span></div>
<div class="line"><a id="l00494" name="l00494"></a><span class="lineno">  494</span>  uint32_t BreakAFMode;           </div>
<div class="line"><a id="l00504" name="l00504"></a><span class="lineno">  504</span> </div>
<div class="line"><a id="l00505" name="l00505"></a><span class="lineno">  505</span><span class="preprocessor">#endif </span><span class="comment">/*TIM_BDTR_BKBID */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00506" name="l00506"></a><span class="lineno">  506</span>  uint32_t Break2State;          </div>
<div class="line"><a id="l00514" name="l00514"></a><span class="lineno">  514</span> </div>
<div class="line"><a id="l00515" name="l00515"></a><span class="lineno">  515</span>  uint32_t Break2Polarity;        </div>
<div class="line"><a id="l00523" name="l00523"></a><span class="lineno">  523</span> </div>
<div class="line"><a id="l00524" name="l00524"></a><span class="lineno">  524</span>  uint32_t Break2Filter;          </div>
<div class="line"><a id="l00532" name="l00532"></a><span class="lineno">  532</span> </div>
<div class="line"><a id="l00533" name="l00533"></a><span class="lineno">  533</span><span class="preprocessor">#if defined(TIM_BDTR_BKBID)</span></div>
<div class="line"><a id="l00534" name="l00534"></a><span class="lineno">  534</span>  uint32_t Break2AFMode;          </div>
<div class="line"><a id="l00544" name="l00544"></a><span class="lineno">  544</span> </div>
<div class="line"><a id="l00545" name="l00545"></a><span class="lineno">  545</span><span class="preprocessor">#endif </span><span class="comment">/*TIM_BDTR_BKBID */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00546" name="l00546"></a><span class="lineno">  546</span>  uint32_t AutomaticOutput;      </div>
<div class="line"><a id="l00554" name="l00554"></a><span class="lineno">  554</span>} LL_TIM_BDTR_InitTypeDef;</div>
<div class="line"><a id="l00555" name="l00555"></a><span class="lineno">  555</span></div>
<div class="line"><a id="l00559" name="l00559"></a><span class="lineno">  559</span><span class="preprocessor">#endif </span><span class="comment">/* USE_FULL_LL_DRIVER */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00560" name="l00560"></a><span class="lineno">  560</span> </div>
<div class="line"><a id="l00561" name="l00561"></a><span class="lineno">  561</span><span class="comment">/* Exported constants --------------------------------------------------------*/</span></div>
<div class="line"><a id="l00565" name="l00565"></a><span class="lineno">  565</span></div>
<div class="line"><a id="l00570" name="l00570"></a><span class="lineno">  570</span><span class="preprocessor">#define LL_TIM_SR_UIF                          TIM_SR_UIF           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00571" name="l00571"></a><span class="lineno">  571</span><span class="preprocessor">#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00572" name="l00572"></a><span class="lineno">  572</span><span class="preprocessor">#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00573" name="l00573"></a><span class="lineno">  573</span><span class="preprocessor">#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00574" name="l00574"></a><span class="lineno">  574</span><span class="preprocessor">#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00575" name="l00575"></a><span class="lineno">  575</span><span class="preprocessor">#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00576" name="l00576"></a><span class="lineno">  576</span><span class="preprocessor">#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00577" name="l00577"></a><span class="lineno">  577</span><span class="preprocessor">#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00578" name="l00578"></a><span class="lineno">  578</span><span class="preprocessor">#define LL_TIM_SR_TIF                          TIM_SR_TIF           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00579" name="l00579"></a><span class="lineno">  579</span><span class="preprocessor">#define LL_TIM_SR_BIF                          TIM_SR_BIF           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00580" name="l00580"></a><span class="lineno">  580</span><span class="preprocessor">#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00581" name="l00581"></a><span class="lineno">  581</span><span class="preprocessor">#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00582" name="l00582"></a><span class="lineno">  582</span><span class="preprocessor">#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00583" name="l00583"></a><span class="lineno">  583</span><span class="preprocessor">#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00584" name="l00584"></a><span class="lineno">  584</span><span class="preprocessor">#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00585" name="l00585"></a><span class="lineno">  585</span><span class="preprocessor">#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00589" name="l00589"></a><span class="lineno">  589</span> </div>
<div class="line"><a id="l00590" name="l00590"></a><span class="lineno">  590</span><span class="preprocessor">#if defined(USE_FULL_LL_DRIVER)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00594" name="l00594"></a><span class="lineno">  594</span><span class="preprocessor">#define LL_TIM_BREAK_DISABLE            0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00595" name="l00595"></a><span class="lineno">  595</span><span class="preprocessor">#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00599" name="l00599"></a><span class="lineno">  599</span></div>
<div class="line"><a id="l00603" name="l00603"></a><span class="lineno">  603</span><span class="preprocessor">#define LL_TIM_BREAK2_DISABLE            0x00000000U              </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00604" name="l00604"></a><span class="lineno">  604</span><span class="preprocessor">#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00608" name="l00608"></a><span class="lineno">  608</span></div>
<div class="line"><a id="l00612" name="l00612"></a><span class="lineno">  612</span><span class="preprocessor">#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00613" name="l00613"></a><span class="lineno">  613</span><span class="preprocessor">#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00617" name="l00617"></a><span class="lineno">  617</span><span class="preprocessor">#endif </span><span class="comment">/* USE_FULL_LL_DRIVER */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00618" name="l00618"></a><span class="lineno">  618</span></div>
<div class="line"><a id="l00623" name="l00623"></a><span class="lineno">  623</span><span class="preprocessor">#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00624" name="l00624"></a><span class="lineno">  624</span><span class="preprocessor">#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00625" name="l00625"></a><span class="lineno">  625</span><span class="preprocessor">#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00626" name="l00626"></a><span class="lineno">  626</span><span class="preprocessor">#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00627" name="l00627"></a><span class="lineno">  627</span><span class="preprocessor">#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00628" name="l00628"></a><span class="lineno">  628</span><span class="preprocessor">#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00629" name="l00629"></a><span class="lineno">  629</span><span class="preprocessor">#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00630" name="l00630"></a><span class="lineno">  630</span><span class="preprocessor">#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00634" name="l00634"></a><span class="lineno">  634</span></div>
<div class="line"><a id="l00638" name="l00638"></a><span class="lineno">  638</span><span class="preprocessor">#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00639" name="l00639"></a><span class="lineno">  639</span><span class="preprocessor">#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00643" name="l00643"></a><span class="lineno">  643</span></div>
<div class="line"><a id="l00647" name="l00647"></a><span class="lineno">  647</span><span class="preprocessor">#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00648" name="l00648"></a><span class="lineno">  648</span><span class="preprocessor">#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00652" name="l00652"></a><span class="lineno">  652</span></div>
<div class="line"><a id="l00656" name="l00656"></a><span class="lineno">  656</span><span class="preprocessor">#define LL_TIM_COUNTERMODE_UP                  0x00000000U          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00657" name="l00657"></a><span class="lineno">  657</span><span class="preprocessor">#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00658" name="l00658"></a><span class="lineno">  658</span><span class="preprocessor">#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00659" name="l00659"></a><span class="lineno">  659</span><span class="preprocessor">#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00660" name="l00660"></a><span class="lineno">  660</span><span class="preprocessor">#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00664" name="l00664"></a><span class="lineno">  664</span></div>
<div class="line"><a id="l00668" name="l00668"></a><span class="lineno">  668</span><span class="preprocessor">#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00669" name="l00669"></a><span class="lineno">  669</span><span class="preprocessor">#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00670" name="l00670"></a><span class="lineno">  670</span><span class="preprocessor">#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00674" name="l00674"></a><span class="lineno">  674</span></div>
<div class="line"><a id="l00678" name="l00678"></a><span class="lineno">  678</span><span class="preprocessor">#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00679" name="l00679"></a><span class="lineno">  679</span><span class="preprocessor">#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00683" name="l00683"></a><span class="lineno">  683</span></div>
<div class="line"><a id="l00687" name="l00687"></a><span class="lineno">  687</span><span class="preprocessor">#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00688" name="l00688"></a><span class="lineno">  688</span><span class="preprocessor">#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00692" name="l00692"></a><span class="lineno">  692</span></div>
<div class="line"><a id="l00696" name="l00696"></a><span class="lineno">  696</span><span class="preprocessor">#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00697" name="l00697"></a><span class="lineno">  697</span><span class="preprocessor">#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00701" name="l00701"></a><span class="lineno">  701</span></div>
<div class="line"><a id="l00705" name="l00705"></a><span class="lineno">  705</span><span class="preprocessor">#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00706" name="l00706"></a><span class="lineno">  706</span><span class="preprocessor">#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00707" name="l00707"></a><span class="lineno">  707</span><span class="preprocessor">#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00708" name="l00708"></a><span class="lineno">  708</span><span class="preprocessor">#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00712" name="l00712"></a><span class="lineno">  712</span></div>
<div class="line"><a id="l00716" name="l00716"></a><span class="lineno">  716</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00717" name="l00717"></a><span class="lineno">  717</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00718" name="l00718"></a><span class="lineno">  718</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00719" name="l00719"></a><span class="lineno">  719</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00720" name="l00720"></a><span class="lineno">  720</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00721" name="l00721"></a><span class="lineno">  721</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00722" name="l00722"></a><span class="lineno">  722</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00723" name="l00723"></a><span class="lineno">  723</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00724" name="l00724"></a><span class="lineno">  724</span><span class="preprocessor">#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00728" name="l00728"></a><span class="lineno">  728</span> </div>
<div class="line"><a id="l00729" name="l00729"></a><span class="lineno">  729</span><span class="preprocessor">#if defined(USE_FULL_LL_DRIVER)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00733" name="l00733"></a><span class="lineno">  733</span><span class="preprocessor">#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00734" name="l00734"></a><span class="lineno">  734</span><span class="preprocessor">#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00738" name="l00738"></a><span class="lineno">  738</span><span class="preprocessor">#endif </span><span class="comment">/* USE_FULL_LL_DRIVER */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00739" name="l00739"></a><span class="lineno">  739</span></div>
<div class="line"><a id="l00743" name="l00743"></a><span class="lineno">  743</span><span class="preprocessor">#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1</span></div>
<div class="line"><a id="l00744" name="l00744"></a><span class="lineno">  744</span><span class="preprocessor">#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00748" name="l00748"></a><span class="lineno">  748</span></div>
<div class="line"><a id="l00752" name="l00752"></a><span class="lineno">  752</span><span class="preprocessor">#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00753" name="l00753"></a><span class="lineno">  753</span><span class="preprocessor">#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00754" name="l00754"></a><span class="lineno">  754</span><span class="preprocessor">#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00755" name="l00755"></a><span class="lineno">  755</span><span class="preprocessor">#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00756" name="l00756"></a><span class="lineno">  756</span><span class="preprocessor">#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00757" name="l00757"></a><span class="lineno">  757</span><span class="preprocessor">#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00758" name="l00758"></a><span class="lineno">  758</span><span class="preprocessor">#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00759" name="l00759"></a><span class="lineno">  759</span><span class="preprocessor">#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00760" name="l00760"></a><span class="lineno">  760</span><span class="preprocessor">#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00761" name="l00761"></a><span class="lineno">  761</span><span class="preprocessor">#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00762" name="l00762"></a><span class="lineno">  762</span><span class="preprocessor">#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00763" name="l00763"></a><span class="lineno">  763</span><span class="preprocessor">#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00764" name="l00764"></a><span class="lineno">  764</span><span class="preprocessor">#define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00765" name="l00765"></a><span class="lineno">  765</span><span class="preprocessor">#define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00769" name="l00769"></a><span class="lineno">  769</span></div>
<div class="line"><a id="l00773" name="l00773"></a><span class="lineno">  773</span><span class="preprocessor">#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00774" name="l00774"></a><span class="lineno">  774</span><span class="preprocessor">#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00778" name="l00778"></a><span class="lineno">  778</span></div>
<div class="line"><a id="l00782" name="l00782"></a><span class="lineno">  782</span><span class="preprocessor">#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00783" name="l00783"></a><span class="lineno">  783</span><span class="preprocessor">#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00787" name="l00787"></a><span class="lineno">  787</span></div>
<div class="line"><a id="l00791" name="l00791"></a><span class="lineno">  791</span><span class="preprocessor">#define LL_TIM_GROUPCH5_NONE                   0x00000000U           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00792" name="l00792"></a><span class="lineno">  792</span><span class="preprocessor">#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00793" name="l00793"></a><span class="lineno">  793</span><span class="preprocessor">#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00794" name="l00794"></a><span class="lineno">  794</span><span class="preprocessor">#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00798" name="l00798"></a><span class="lineno">  798</span></div>
<div class="line"><a id="l00802" name="l00802"></a><span class="lineno">  802</span><span class="preprocessor">#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 &lt;&lt; 16U) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00803" name="l00803"></a><span class="lineno">  803</span><span class="preprocessor">#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 &lt;&lt; 16U) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00804" name="l00804"></a><span class="lineno">  804</span><span class="preprocessor">#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S &lt;&lt; 16U)   </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00808" name="l00808"></a><span class="lineno">  808</span></div>
<div class="line"><a id="l00812" name="l00812"></a><span class="lineno">  812</span><span class="preprocessor">#define LL_TIM_ICPSC_DIV1                      0x00000000U                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00813" name="l00813"></a><span class="lineno">  813</span><span class="preprocessor">#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 &lt;&lt; 16U)    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00814" name="l00814"></a><span class="lineno">  814</span><span class="preprocessor">#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 &lt;&lt; 16U)    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00815" name="l00815"></a><span class="lineno">  815</span><span class="preprocessor">#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC &lt;&lt; 16U)      </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00819" name="l00819"></a><span class="lineno">  819</span></div>
<div class="line"><a id="l00823" name="l00823"></a><span class="lineno">  823</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00824" name="l00824"></a><span class="lineno">  824</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 &lt;&lt; 16U)                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00825" name="l00825"></a><span class="lineno">  825</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 &lt;&lt; 16U)                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00826" name="l00826"></a><span class="lineno">  826</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) &lt;&lt; 16U)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00827" name="l00827"></a><span class="lineno">  827</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 &lt;&lt; 16U)                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00828" name="l00828"></a><span class="lineno">  828</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) &lt;&lt; 16U)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00829" name="l00829"></a><span class="lineno">  829</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) &lt;&lt; 16U)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00830" name="l00830"></a><span class="lineno">  830</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) &lt;&lt; 16U)  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00831" name="l00831"></a><span class="lineno">  831</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 &lt;&lt; 16U)                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00832" name="l00832"></a><span class="lineno">  832</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) &lt;&lt; 16U)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00833" name="l00833"></a><span class="lineno">  833</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) &lt;&lt; 16U)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00834" name="l00834"></a><span class="lineno">  834</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) &lt;&lt; 16U)  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00835" name="l00835"></a><span class="lineno">  835</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) &lt;&lt; 16U)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00836" name="l00836"></a><span class="lineno">  836</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) &lt;&lt; 16U)  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00837" name="l00837"></a><span class="lineno">  837</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) &lt;&lt; 16U)  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00838" name="l00838"></a><span class="lineno">  838</span><span class="preprocessor">#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F &lt;&lt; 16U)                                            </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00842" name="l00842"></a><span class="lineno">  842</span></div>
<div class="line"><a id="l00846" name="l00846"></a><span class="lineno">  846</span><span class="preprocessor">#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00847" name="l00847"></a><span class="lineno">  847</span><span class="preprocessor">#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00848" name="l00848"></a><span class="lineno">  848</span><span class="preprocessor">#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00852" name="l00852"></a><span class="lineno">  852</span></div>
<div class="line"><a id="l00856" name="l00856"></a><span class="lineno">  856</span><span class="preprocessor">#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00857" name="l00857"></a><span class="lineno">  857</span><span class="preprocessor">#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00858" name="l00858"></a><span class="lineno">  858</span><span class="preprocessor">#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00862" name="l00862"></a><span class="lineno">  862</span></div>
<div class="line"><a id="l00866" name="l00866"></a><span class="lineno">  866</span><span class="preprocessor">#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00867" name="l00867"></a><span class="lineno">  867</span><span class="preprocessor">#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00868" name="l00868"></a><span class="lineno">  868</span><span class="preprocessor">#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00872" name="l00872"></a><span class="lineno">  872</span></div>
<div class="line"><a id="l00876" name="l00876"></a><span class="lineno">  876</span><span class="preprocessor">#define LL_TIM_TRGO_RESET                      0x00000000U                                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00877" name="l00877"></a><span class="lineno">  877</span><span class="preprocessor">#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00878" name="l00878"></a><span class="lineno">  878</span><span class="preprocessor">#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00879" name="l00879"></a><span class="lineno">  879</span><span class="preprocessor">#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00880" name="l00880"></a><span class="lineno">  880</span><span class="preprocessor">#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00881" name="l00881"></a><span class="lineno">  881</span><span class="preprocessor">#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00882" name="l00882"></a><span class="lineno">  882</span><span class="preprocessor">#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00883" name="l00883"></a><span class="lineno">  883</span><span class="preprocessor">#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00887" name="l00887"></a><span class="lineno">  887</span></div>
<div class="line"><a id="l00891" name="l00891"></a><span class="lineno">  891</span><span class="preprocessor">#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00892" name="l00892"></a><span class="lineno">  892</span><span class="preprocessor">#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00893" name="l00893"></a><span class="lineno">  893</span><span class="preprocessor">#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00894" name="l00894"></a><span class="lineno">  894</span><span class="preprocessor">#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00895" name="l00895"></a><span class="lineno">  895</span><span class="preprocessor">#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00896" name="l00896"></a><span class="lineno">  896</span><span class="preprocessor">#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00897" name="l00897"></a><span class="lineno">  897</span><span class="preprocessor">#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00898" name="l00898"></a><span class="lineno">  898</span><span class="preprocessor">#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00899" name="l00899"></a><span class="lineno">  899</span><span class="preprocessor">#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00900" name="l00900"></a><span class="lineno">  900</span><span class="preprocessor">#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00901" name="l00901"></a><span class="lineno">  901</span><span class="preprocessor">#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00902" name="l00902"></a><span class="lineno">  902</span><span class="preprocessor">#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00903" name="l00903"></a><span class="lineno">  903</span><span class="preprocessor">#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00904" name="l00904"></a><span class="lineno">  904</span><span class="preprocessor">#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00905" name="l00905"></a><span class="lineno">  905</span><span class="preprocessor">#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00906" name="l00906"></a><span class="lineno">  906</span><span class="preprocessor">#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00910" name="l00910"></a><span class="lineno">  910</span></div>
<div class="line"><a id="l00914" name="l00914"></a><span class="lineno">  914</span><span class="preprocessor">#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00915" name="l00915"></a><span class="lineno">  915</span><span class="preprocessor">#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00916" name="l00916"></a><span class="lineno">  916</span><span class="preprocessor">#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00917" name="l00917"></a><span class="lineno">  917</span><span class="preprocessor">#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00918" name="l00918"></a><span class="lineno">  918</span><span class="preprocessor">#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00922" name="l00922"></a><span class="lineno">  922</span></div>
<div class="line"><a id="l00926" name="l00926"></a><span class="lineno">  926</span><span class="preprocessor">#define LL_TIM_TS_ITR0                         0x00000000U                                                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00927" name="l00927"></a><span class="lineno">  927</span><span class="preprocessor">#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00928" name="l00928"></a><span class="lineno">  928</span><span class="preprocessor">#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00929" name="l00929"></a><span class="lineno">  929</span><span class="preprocessor">#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00930" name="l00930"></a><span class="lineno">  930</span><span class="preprocessor">#define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00931" name="l00931"></a><span class="lineno">  931</span><span class="preprocessor">#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00932" name="l00932"></a><span class="lineno">  932</span><span class="preprocessor">#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00933" name="l00933"></a><span class="lineno">  933</span><span class="preprocessor">#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00934" name="l00934"></a><span class="lineno">  934</span><span class="preprocessor">#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00935" name="l00935"></a><span class="lineno">  935</span><span class="preprocessor">#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00936" name="l00936"></a><span class="lineno">  936</span><span class="preprocessor">#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00937" name="l00937"></a><span class="lineno">  937</span><span class="preprocessor">#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00938" name="l00938"></a><span class="lineno">  938</span><span class="preprocessor">#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00939" name="l00939"></a><span class="lineno">  939</span><span class="preprocessor">#define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00940" name="l00940"></a><span class="lineno">  940</span><span class="preprocessor">#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00941" name="l00941"></a><span class="lineno">  941</span><span class="preprocessor">#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00942" name="l00942"></a><span class="lineno">  942</span><span class="preprocessor">#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00943" name="l00943"></a><span class="lineno">  943</span><span class="preprocessor">#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00947" name="l00947"></a><span class="lineno">  947</span></div>
<div class="line"><a id="l00951" name="l00951"></a><span class="lineno">  951</span><span class="preprocessor">#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00952" name="l00952"></a><span class="lineno">  952</span><span class="preprocessor">#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00956" name="l00956"></a><span class="lineno">  956</span></div>
<div class="line"><a id="l00960" name="l00960"></a><span class="lineno">  960</span><span class="preprocessor">#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00961" name="l00961"></a><span class="lineno">  961</span><span class="preprocessor">#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00962" name="l00962"></a><span class="lineno">  962</span><span class="preprocessor">#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00963" name="l00963"></a><span class="lineno">  963</span><span class="preprocessor">#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00967" name="l00967"></a><span class="lineno">  967</span></div>
<div class="line"><a id="l00971" name="l00971"></a><span class="lineno">  971</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00972" name="l00972"></a><span class="lineno">  972</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00973" name="l00973"></a><span class="lineno">  973</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00974" name="l00974"></a><span class="lineno">  974</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00975" name="l00975"></a><span class="lineno">  975</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00976" name="l00976"></a><span class="lineno">  976</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00977" name="l00977"></a><span class="lineno">  977</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00978" name="l00978"></a><span class="lineno">  978</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00979" name="l00979"></a><span class="lineno">  979</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00980" name="l00980"></a><span class="lineno">  980</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00981" name="l00981"></a><span class="lineno">  981</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00982" name="l00982"></a><span class="lineno">  982</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00983" name="l00983"></a><span class="lineno">  983</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00984" name="l00984"></a><span class="lineno">  984</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00985" name="l00985"></a><span class="lineno">  985</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00986" name="l00986"></a><span class="lineno">  986</span><span class="preprocessor">#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00990" name="l00990"></a><span class="lineno">  990</span> </div>
<div class="line"><a id="l00991" name="l00991"></a><span class="lineno">  991</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00992" name="l00992"></a><span class="lineno">  992</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00993" name="l00993"></a><span class="lineno">  993</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00994" name="l00994"></a><span class="lineno">  994</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00995" name="l00995"></a><span class="lineno">  995</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00996" name="l00996"></a><span class="lineno">  996</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00997" name="l00997"></a><span class="lineno">  997</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00998" name="l00998"></a><span class="lineno">  998</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00999" name="l00999"></a><span class="lineno">  999</span><span class="preprocessor">#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01000" name="l01000"></a><span class="lineno"> 1000</span> </div>
<div class="line"><a id="l01001" name="l01001"></a><span class="lineno"> 1001</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01002" name="l01002"></a><span class="lineno"> 1002</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01003" name="l01003"></a><span class="lineno"> 1003</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01004" name="l01004"></a><span class="lineno"> 1004</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01005" name="l01005"></a><span class="lineno"> 1005</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01006" name="l01006"></a><span class="lineno"> 1006</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01007" name="l01007"></a><span class="lineno"> 1007</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01008" name="l01008"></a><span class="lineno"> 1008</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01009" name="l01009"></a><span class="lineno"> 1009</span><span class="preprocessor">#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01010" name="l01010"></a><span class="lineno"> 1010</span> </div>
<div class="line"><a id="l01011" name="l01011"></a><span class="lineno"> 1011</span><span class="preprocessor">#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01012" name="l01012"></a><span class="lineno"> 1012</span><span class="preprocessor">#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01013" name="l01013"></a><span class="lineno"> 1013</span><span class="preprocessor">#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01014" name="l01014"></a><span class="lineno"> 1014</span><span class="preprocessor">#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01015" name="l01015"></a><span class="lineno"> 1015</span><span class="preprocessor">#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01016" name="l01016"></a><span class="lineno"> 1016</span><span class="preprocessor">#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01017" name="l01017"></a><span class="lineno"> 1017</span> </div>
<div class="line"><a id="l01018" name="l01018"></a><span class="lineno"> 1018</span><span class="preprocessor">#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01019" name="l01019"></a><span class="lineno"> 1019</span><span class="preprocessor">#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01020" name="l01020"></a><span class="lineno"> 1020</span> </div>
<div class="line"><a id="l01021" name="l01021"></a><span class="lineno"> 1021</span><span class="preprocessor">#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01022" name="l01022"></a><span class="lineno"> 1022</span><span class="preprocessor">#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01023" name="l01023"></a><span class="lineno"> 1023</span><span class="preprocessor">#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01024" name="l01024"></a><span class="lineno"> 1024</span><span class="preprocessor">#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01025" name="l01025"></a><span class="lineno"> 1025</span><span class="preprocessor">#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01026" name="l01026"></a><span class="lineno"> 1026</span> </div>
<div class="line"><a id="l01027" name="l01027"></a><span class="lineno"> 1027</span><span class="preprocessor">#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01028" name="l01028"></a><span class="lineno"> 1028</span><span class="preprocessor">#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01029" name="l01029"></a><span class="lineno"> 1029</span><span class="preprocessor">#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01030" name="l01030"></a><span class="lineno"> 1030</span> </div>
<div class="line"><a id="l01031" name="l01031"></a><span class="lineno"> 1031</span><span class="preprocessor">#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01032" name="l01032"></a><span class="lineno"> 1032</span><span class="preprocessor">#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01033" name="l01033"></a><span class="lineno"> 1033</span><span class="preprocessor">#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01034" name="l01034"></a><span class="lineno"> 1034</span><span class="preprocessor">#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01035" name="l01035"></a><span class="lineno"> 1035</span><span class="preprocessor">#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01036" name="l01036"></a><span class="lineno"> 1036</span></div>
<div class="line"><a id="l01040" name="l01040"></a><span class="lineno"> 1040</span><span class="preprocessor">#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01041" name="l01041"></a><span class="lineno"> 1041</span><span class="preprocessor">#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01045" name="l01045"></a><span class="lineno"> 1045</span></div>
<div class="line"><a id="l01049" name="l01049"></a><span class="lineno"> 1049</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01050" name="l01050"></a><span class="lineno"> 1050</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01051" name="l01051"></a><span class="lineno"> 1051</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01052" name="l01052"></a><span class="lineno"> 1052</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01053" name="l01053"></a><span class="lineno"> 1053</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01054" name="l01054"></a><span class="lineno"> 1054</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01055" name="l01055"></a><span class="lineno"> 1055</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01056" name="l01056"></a><span class="lineno"> 1056</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01057" name="l01057"></a><span class="lineno"> 1057</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01058" name="l01058"></a><span class="lineno"> 1058</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01059" name="l01059"></a><span class="lineno"> 1059</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01060" name="l01060"></a><span class="lineno"> 1060</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01061" name="l01061"></a><span class="lineno"> 1061</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01062" name="l01062"></a><span class="lineno"> 1062</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01063" name="l01063"></a><span class="lineno"> 1063</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01064" name="l01064"></a><span class="lineno"> 1064</span><span class="preprocessor">#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01068" name="l01068"></a><span class="lineno"> 1068</span></div>
<div class="line"><a id="l01072" name="l01072"></a><span class="lineno"> 1072</span><span class="preprocessor">#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01073" name="l01073"></a><span class="lineno"> 1073</span><span class="preprocessor">#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01077" name="l01077"></a><span class="lineno"> 1077</span></div>
<div class="line"><a id="l01081" name="l01081"></a><span class="lineno"> 1081</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01082" name="l01082"></a><span class="lineno"> 1082</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01083" name="l01083"></a><span class="lineno"> 1083</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01084" name="l01084"></a><span class="lineno"> 1084</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01085" name="l01085"></a><span class="lineno"> 1085</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01086" name="l01086"></a><span class="lineno"> 1086</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01087" name="l01087"></a><span class="lineno"> 1087</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01088" name="l01088"></a><span class="lineno"> 1088</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01089" name="l01089"></a><span class="lineno"> 1089</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01090" name="l01090"></a><span class="lineno"> 1090</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01091" name="l01091"></a><span class="lineno"> 1091</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01092" name="l01092"></a><span class="lineno"> 1092</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01093" name="l01093"></a><span class="lineno"> 1093</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01094" name="l01094"></a><span class="lineno"> 1094</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01095" name="l01095"></a><span class="lineno"> 1095</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01096" name="l01096"></a><span class="lineno"> 1096</span><span class="preprocessor">#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01100" name="l01100"></a><span class="lineno"> 1100</span></div>
<div class="line"><a id="l01104" name="l01104"></a><span class="lineno"> 1104</span><span class="preprocessor">#define LL_TIM_OSSI_DISABLE                    0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01105" name="l01105"></a><span class="lineno"> 1105</span><span class="preprocessor">#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01109" name="l01109"></a><span class="lineno"> 1109</span></div>
<div class="line"><a id="l01113" name="l01113"></a><span class="lineno"> 1113</span><span class="preprocessor">#define LL_TIM_OSSR_DISABLE                    0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01114" name="l01114"></a><span class="lineno"> 1114</span><span class="preprocessor">#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01118" name="l01118"></a><span class="lineno"> 1118</span> </div>
<div class="line"><a id="l01119" name="l01119"></a><span class="lineno"> 1119</span><span class="preprocessor">#if   defined(TIM_BREAK_INPUT_SUPPORT)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01123" name="l01123"></a><span class="lineno"> 1123</span><span class="preprocessor">#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01124" name="l01124"></a><span class="lineno"> 1124</span><span class="preprocessor">#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01128" name="l01128"></a><span class="lineno"> 1128</span></div>
<div class="line"><a id="l01132" name="l01132"></a><span class="lineno"> 1132</span><span class="preprocessor">#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01133" name="l01133"></a><span class="lineno"> 1133</span><span class="preprocessor">#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01134" name="l01134"></a><span class="lineno"> 1134</span><span class="preprocessor">#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01135" name="l01135"></a><span class="lineno"> 1135</span><span class="preprocessor">#define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01139" name="l01139"></a><span class="lineno"> 1139</span></div>
<div class="line"><a id="l01143" name="l01143"></a><span class="lineno"> 1143</span><span class="preprocessor">#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01144" name="l01144"></a><span class="lineno"> 1144</span><span class="preprocessor">#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01148" name="l01148"></a><span class="lineno"> 1148</span><span class="preprocessor">#endif </span><span class="comment">/* TIM_BREAK_INPUT_SUPPORT */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01149" name="l01149"></a><span class="lineno"> 1149</span> </div>
<div class="line"><a id="l01150" name="l01150"></a><span class="lineno"> 1150</span><span class="preprocessor">#if defined(TIM_BDTR_BKBID)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01154" name="l01154"></a><span class="lineno"> 1154</span><span class="preprocessor">#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01155" name="l01155"></a><span class="lineno"> 1155</span><span class="preprocessor">#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01159" name="l01159"></a><span class="lineno"> 1159</span></div>
<div class="line"><a id="l01163" name="l01163"></a><span class="lineno"> 1163</span><span class="preprocessor">#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01164" name="l01164"></a><span class="lineno"> 1164</span><span class="preprocessor">#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01168" name="l01168"></a><span class="lineno"> 1168</span></div>
<div class="line"><a id="l01172" name="l01172"></a><span class="lineno"> 1172</span><span class="preprocessor">#define LL_TIM_ReArmBRK(_PARAM_)</span></div>
<div class="line"><a id="l01173" name="l01173"></a><span class="lineno"> 1173</span><span class="preprocessor">#define LL_TIM_ReArmBRK2(_PARAM_)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01177" name="l01177"></a><span class="lineno"> 1177</span> </div>
<div class="line"><a id="l01178" name="l01178"></a><span class="lineno"> 1178</span><span class="preprocessor">#endif </span><span class="comment">/*TIM_BDTR_BKBID */</span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01182" name="l01182"></a><span class="lineno"> 1182</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01183" name="l01183"></a><span class="lineno"> 1183</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01184" name="l01184"></a><span class="lineno"> 1184</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01185" name="l01185"></a><span class="lineno"> 1185</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01186" name="l01186"></a><span class="lineno"> 1186</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01187" name="l01187"></a><span class="lineno"> 1187</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01188" name="l01188"></a><span class="lineno"> 1188</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01189" name="l01189"></a><span class="lineno"> 1189</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01190" name="l01190"></a><span class="lineno"> 1190</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01191" name="l01191"></a><span class="lineno"> 1191</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01192" name="l01192"></a><span class="lineno"> 1192</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01193" name="l01193"></a><span class="lineno"> 1193</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01194" name="l01194"></a><span class="lineno"> 1194</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01195" name="l01195"></a><span class="lineno"> 1195</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01196" name="l01196"></a><span class="lineno"> 1196</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01197" name="l01197"></a><span class="lineno"> 1197</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01198" name="l01198"></a><span class="lineno"> 1198</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01199" name="l01199"></a><span class="lineno"> 1199</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01200" name="l01200"></a><span class="lineno"> 1200</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01201" name="l01201"></a><span class="lineno"> 1201</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01202" name="l01202"></a><span class="lineno"> 1202</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01203" name="l01203"></a><span class="lineno"> 1203</span><span class="preprocessor">#if defined(TIM1_AF1_BKINE)&amp;&amp;defined(TIM1_AF2_BKINE)</span></div>
<div class="line"><a id="l01204" name="l01204"></a><span class="lineno"> 1204</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01205" name="l01205"></a><span class="lineno"> 1205</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01206" name="l01206"></a><span class="lineno"> 1206</span><span class="preprocessor">#endif </span><span class="comment">/* TIM1_AF1_BKINE &amp;&amp; TIM1_AF2_BKINE */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01207" name="l01207"></a><span class="lineno"> 1207</span><span class="preprocessor">#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01211" name="l01211"></a><span class="lineno"> 1211</span></div>
<div class="line"><a id="l01215" name="l01215"></a><span class="lineno"> 1215</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01216" name="l01216"></a><span class="lineno"> 1216</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01217" name="l01217"></a><span class="lineno"> 1217</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01218" name="l01218"></a><span class="lineno"> 1218</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01219" name="l01219"></a><span class="lineno"> 1219</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01220" name="l01220"></a><span class="lineno"> 1220</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01221" name="l01221"></a><span class="lineno"> 1221</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01222" name="l01222"></a><span class="lineno"> 1222</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01223" name="l01223"></a><span class="lineno"> 1223</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01224" name="l01224"></a><span class="lineno"> 1224</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01225" name="l01225"></a><span class="lineno"> 1225</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01226" name="l01226"></a><span class="lineno"> 1226</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01227" name="l01227"></a><span class="lineno"> 1227</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01228" name="l01228"></a><span class="lineno"> 1228</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01229" name="l01229"></a><span class="lineno"> 1229</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01230" name="l01230"></a><span class="lineno"> 1230</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01231" name="l01231"></a><span class="lineno"> 1231</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01232" name="l01232"></a><span class="lineno"> 1232</span><span class="preprocessor">#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01236" name="l01236"></a><span class="lineno"> 1236</span></div>
<div class="line"><a id="l01240" name="l01240"></a><span class="lineno"> 1240</span><span class="preprocessor">#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01241" name="l01241"></a><span class="lineno"> 1241</span><span class="preprocessor">#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01245" name="l01245"></a><span class="lineno"> 1245</span></div>
<div class="line"><a id="l01249" name="l01249"></a><span class="lineno"> 1249</span><span class="preprocessor">#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01250" name="l01250"></a><span class="lineno"> 1250</span><span class="preprocessor">#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01254" name="l01254"></a><span class="lineno"> 1254</span></div>
<div class="line"><a id="l01258" name="l01258"></a><span class="lineno"> 1258</span><span class="preprocessor">#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01259" name="l01259"></a><span class="lineno"> 1259</span><span class="preprocessor">#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01260" name="l01260"></a><span class="lineno"> 1260</span><span class="preprocessor">#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01261" name="l01261"></a><span class="lineno"> 1261</span><span class="preprocessor">#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01265" name="l01265"></a><span class="lineno"> 1265</span></div>
<div class="line"><a id="l01269" name="l01269"></a><span class="lineno"> 1269</span><span class="preprocessor">#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01270" name="l01270"></a><span class="lineno"> 1270</span><span class="preprocessor">#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01271" name="l01271"></a><span class="lineno"> 1271</span><span class="preprocessor">#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01272" name="l01272"></a><span class="lineno"> 1272</span><span class="preprocessor">#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01276" name="l01276"></a><span class="lineno"> 1276</span></div>
<div class="line"><a id="l01280" name="l01280"></a><span class="lineno"> 1280</span><span class="preprocessor">#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01281" name="l01281"></a><span class="lineno"> 1281</span><span class="preprocessor">#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01282" name="l01282"></a><span class="lineno"> 1282</span><span class="preprocessor">#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01286" name="l01286"></a><span class="lineno"> 1286</span></div>
<div class="line"><a id="l01290" name="l01290"></a><span class="lineno"> 1290</span><span class="preprocessor">#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01291" name="l01291"></a><span class="lineno"> 1291</span><span class="preprocessor">#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01295" name="l01295"></a><span class="lineno"> 1295</span></div>
<div class="line"><a id="l01299" name="l01299"></a><span class="lineno"> 1299</span><span class="preprocessor">#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01300" name="l01300"></a><span class="lineno"> 1300</span><span class="preprocessor">#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01301" name="l01301"></a><span class="lineno"> 1301</span><span class="preprocessor">#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01302" name="l01302"></a><span class="lineno"> 1302</span><span class="preprocessor">#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01303" name="l01303"></a><span class="lineno"> 1303</span><span class="preprocessor">#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01304" name="l01304"></a><span class="lineno"> 1304</span><span class="preprocessor">#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01305" name="l01305"></a><span class="lineno"> 1305</span><span class="preprocessor">#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01309" name="l01309"></a><span class="lineno"> 1309</span></div>
<div class="line"><a id="l01313" name="l01313"></a><span class="lineno"> 1313</span><span class="preprocessor">#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01314" name="l01314"></a><span class="lineno"> 1314</span><span class="preprocessor">#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01315" name="l01315"></a><span class="lineno"> 1315</span><span class="preprocessor">#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01316" name="l01316"></a><span class="lineno"> 1316</span><span class="preprocessor">#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01320" name="l01320"></a><span class="lineno"> 1320</span></div>
<div class="line"><a id="l01324" name="l01324"></a><span class="lineno"> 1324</span><span class="preprocessor">#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01325" name="l01325"></a><span class="lineno"> 1325</span><span class="preprocessor">#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01326" name="l01326"></a><span class="lineno"> 1326</span><span class="preprocessor">#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01327" name="l01327"></a><span class="lineno"> 1327</span><span class="preprocessor">#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01331" name="l01331"></a><span class="lineno"> 1331</span></div>
<div class="line"><a id="l01335" name="l01335"></a><span class="lineno"> 1335</span><span class="preprocessor">#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01336" name="l01336"></a><span class="lineno"> 1336</span><span class="preprocessor">#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01337" name="l01337"></a><span class="lineno"> 1337</span><span class="preprocessor">#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01338" name="l01338"></a><span class="lineno"> 1338</span><span class="preprocessor">#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01342" name="l01342"></a><span class="lineno"> 1342</span></div>
<div class="line"><a id="l01346" name="l01346"></a><span class="lineno"> 1346</span><span class="preprocessor">#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01347" name="l01347"></a><span class="lineno"> 1347</span><span class="preprocessor">#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01348" name="l01348"></a><span class="lineno"> 1348</span><span class="preprocessor">#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01349" name="l01349"></a><span class="lineno"> 1349</span><span class="preprocessor">#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01353" name="l01353"></a><span class="lineno"> 1353</span></div>
<div class="line"><a id="l01357" name="l01357"></a><span class="lineno"> 1357</span><span class="preprocessor">#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01358" name="l01358"></a><span class="lineno"> 1358</span><span class="preprocessor">#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01359" name="l01359"></a><span class="lineno"> 1359</span><span class="preprocessor">#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        </span><span class="preprocessor"></span></div>
<div class="line"><a id="l01360" name="l01360"></a><span class="lineno"> 1360</span><span class="preprocessor">#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l01364" name="l01364"></a><span class="lineno"> 1364</span> </div>
<div class="line"><a id="l01365" name="l01365"></a><span class="lineno"> 1365</span><span class="preprocessor">#if defined(TIM_BREAK_INPUT_SUPPORT)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01369" name="l01369"></a><span class="lineno"> 1369</span><span class="preprocessor">#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01373" name="l01373"></a><span class="lineno"> 1373</span><span class="preprocessor">#endif </span><span class="comment">/* TIM_BREAK_INPUT_SUPPORT */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01374" name="l01374"></a><span class="lineno"> 1374</span></div>
<div class="line"><a id="l01378" name="l01378"></a><span class="lineno"> 1378</span> </div>
<div class="line"><a id="l01379" name="l01379"></a><span class="lineno"> 1379</span><span class="comment">/* Exported macro ------------------------------------------------------------*/</span></div>
<div class="line"><a id="l01383" name="l01383"></a><span class="lineno"> 1383</span></div>
<div class="line"><a id="l01394" name="l01394"></a><span class="lineno"> 1394</span><span class="preprocessor">#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)-&gt;__REG__, (__VALUE__))</span></div>
<div class="line"><a id="l01395" name="l01395"></a><span class="lineno"> 1395</span></div>
<div class="line"><a id="l01402" name="l01402"></a><span class="lineno"> 1402</span><span class="preprocessor">#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)-&gt;__REG__)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l01406" name="l01406"></a><span class="lineno"> 1406</span></div>
<div class="line"><a id="l01415" name="l01415"></a><span class="lineno"> 1415</span><span class="preprocessor">#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \</span></div>
<div class="line"><a id="l01416" name="l01416"></a><span class="lineno"> 1416</span><span class="preprocessor">  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) &gt;&gt; TIM_CNT_UIFCPY_Pos)</span></div>
<div class="line"><a id="l01417" name="l01417"></a><span class="lineno"> 1417</span></div>
<div class="line"><a id="l01429" name="l01429"></a><span class="lineno"> 1429</span><span class="preprocessor">#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \</span></div>
<div class="line"><a id="l01430" name="l01430"></a><span class="lineno"> 1430</span><span class="preprocessor">  ( (((uint64_t)((__DT__)*1000U)) &lt; ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \</span></div>
<div class="line"><a id="l01431" name="l01431"></a><span class="lineno"> 1431</span><span class="preprocessor">    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  &amp; DT_DELAY_1) :      \</span></div>
<div class="line"><a id="l01432" name="l01432"></a><span class="lineno"> 1432</span><span class="preprocessor">    (((uint64_t)((__DT__)*1000U)) &lt; ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \</span></div>
<div class="line"><a id="l01433" name="l01433"></a><span class="lineno"> 1433</span><span class="preprocessor">    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \</span></div>
<div class="line"><a id="l01434" name="l01434"></a><span class="lineno"> 1434</span><span class="preprocessor">                                                 (__CKD__))) &gt;&gt; 1U) - (uint8_t) 64) &amp; DT_DELAY_2)) :\</span></div>
<div class="line"><a id="l01435" name="l01435"></a><span class="lineno"> 1435</span><span class="preprocessor">    (((uint64_t)((__DT__)*1000U)) &lt; ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \</span></div>
<div class="line"><a id="l01436" name="l01436"></a><span class="lineno"> 1436</span><span class="preprocessor">    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \</span></div>
<div class="line"><a id="l01437" name="l01437"></a><span class="lineno"> 1437</span><span class="preprocessor">                                                 (__CKD__))) &gt;&gt; 3U) - (uint8_t) 32) &amp; DT_DELAY_3)) :\</span></div>
<div class="line"><a id="l01438" name="l01438"></a><span class="lineno"> 1438</span><span class="preprocessor">    (((uint64_t)((__DT__)*1000U)) &lt; ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \</span></div>
<div class="line"><a id="l01439" name="l01439"></a><span class="lineno"> 1439</span><span class="preprocessor">    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \</span></div>
<div class="line"><a id="l01440" name="l01440"></a><span class="lineno"> 1440</span><span class="preprocessor">                                                 (__CKD__))) &gt;&gt; 4U) - (uint8_t) 32) &amp; DT_DELAY_4)) :\</span></div>
<div class="line"><a id="l01441" name="l01441"></a><span class="lineno"> 1441</span><span class="preprocessor">    0U)</span></div>
<div class="line"><a id="l01442" name="l01442"></a><span class="lineno"> 1442</span></div>
<div class="line"><a id="l01450" name="l01450"></a><span class="lineno"> 1450</span><span class="preprocessor">#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \</span></div>
<div class="line"><a id="l01451" name="l01451"></a><span class="lineno"> 1451</span><span class="preprocessor">  (((__TIMCLK__) &gt;= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)</span></div>
<div class="line"><a id="l01452" name="l01452"></a><span class="lineno"> 1452</span></div>
<div class="line"><a id="l01461" name="l01461"></a><span class="lineno"> 1461</span><span class="preprocessor">#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \</span></div>
<div class="line"><a id="l01462" name="l01462"></a><span class="lineno"> 1462</span><span class="preprocessor">  ((((__TIMCLK__)/((__PSC__) + 1U)) &gt;= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)</span></div>
<div class="line"><a id="l01463" name="l01463"></a><span class="lineno"> 1463</span></div>
<div class="line"><a id="l01473" name="l01473"></a><span class="lineno"> 1473</span><span class="preprocessor">#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \</span></div>
<div class="line"><a id="l01474" name="l01474"></a><span class="lineno"> 1474</span><span class="preprocessor">  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \</span></div>
<div class="line"><a id="l01475" name="l01475"></a><span class="lineno"> 1475</span><span class="preprocessor">              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))</span></div>
<div class="line"><a id="l01476" name="l01476"></a><span class="lineno"> 1476</span></div>
<div class="line"><a id="l01487" name="l01487"></a><span class="lineno"> 1487</span><span class="preprocessor">#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \</span></div>
<div class="line"><a id="l01488" name="l01488"></a><span class="lineno"> 1488</span><span class="preprocessor">  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \</span></div>
<div class="line"><a id="l01489" name="l01489"></a><span class="lineno"> 1489</span><span class="preprocessor">              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))</span></div>
<div class="line"><a id="l01490" name="l01490"></a><span class="lineno"> 1490</span></div>
<div class="line"><a id="l01501" name="l01501"></a><span class="lineno"> 1501</span><span class="preprocessor">#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \</span></div>
<div class="line"><a id="l01502" name="l01502"></a><span class="lineno"> 1502</span><span class="preprocessor">  ((uint32_t)(0x01U &lt;&lt; (((__ICPSC__) &gt;&gt; 16U) &gt;&gt; TIM_CCMR1_IC1PSC_Pos)))</span></div>
<div class="line"><a id="l01503" name="l01503"></a><span class="lineno"> 1503</span> </div>
<div class="line"><a id="l01504" name="l01504"></a><span class="lineno"> 1504</span></div>
<div class="line"><a id="l01508" name="l01508"></a><span class="lineno"> 1508</span> </div>
<div class="line"><a id="l01509" name="l01509"></a><span class="lineno"> 1509</span><span class="comment">/* Exported functions --------------------------------------------------------*/</span></div>
<div class="line"><a id="l01513" name="l01513"></a><span class="lineno"> 1513</span></div>
<div class="line"><a id="l01523" name="l01523"></a><span class="lineno"> 1523</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableCounter(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01524" name="l01524"></a><span class="lineno"> 1524</span>{</div>
<div class="line"><a id="l01525" name="l01525"></a><span class="lineno"> 1525</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">TIM_CR1_CEN</a>);</div>
<div class="line"><a id="l01526" name="l01526"></a><span class="lineno"> 1526</span>}</div>
<div class="line"><a id="l01527" name="l01527"></a><span class="lineno"> 1527</span></div>
<div class="line"><a id="l01534" name="l01534"></a><span class="lineno"> 1534</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableCounter(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01535" name="l01535"></a><span class="lineno"> 1535</span>{</div>
<div class="line"><a id="l01536" name="l01536"></a><span class="lineno"> 1536</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">TIM_CR1_CEN</a>);</div>
<div class="line"><a id="l01537" name="l01537"></a><span class="lineno"> 1537</span>}</div>
<div class="line"><a id="l01538" name="l01538"></a><span class="lineno"> 1538</span></div>
<div class="line"><a id="l01545" name="l01545"></a><span class="lineno"> 1545</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01546" name="l01546"></a><span class="lineno"> 1546</span>{</div>
<div class="line"><a id="l01547" name="l01547"></a><span class="lineno"> 1547</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">TIM_CR1_CEN</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">TIM_CR1_CEN</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l01548" name="l01548"></a><span class="lineno"> 1548</span>}</div>
<div class="line"><a id="l01549" name="l01549"></a><span class="lineno"> 1549</span></div>
<div class="line"><a id="l01556" name="l01556"></a><span class="lineno"> 1556</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableUpdateEvent(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01557" name="l01557"></a><span class="lineno"> 1557</span>{</div>
<div class="line"><a id="l01558" name="l01558"></a><span class="lineno"> 1558</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c">TIM_CR1_UDIS</a>);</div>
<div class="line"><a id="l01559" name="l01559"></a><span class="lineno"> 1559</span>}</div>
<div class="line"><a id="l01560" name="l01560"></a><span class="lineno"> 1560</span></div>
<div class="line"><a id="l01567" name="l01567"></a><span class="lineno"> 1567</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableUpdateEvent(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01568" name="l01568"></a><span class="lineno"> 1568</span>{</div>
<div class="line"><a id="l01569" name="l01569"></a><span class="lineno"> 1569</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c">TIM_CR1_UDIS</a>);</div>
<div class="line"><a id="l01570" name="l01570"></a><span class="lineno"> 1570</span>}</div>
<div class="line"><a id="l01571" name="l01571"></a><span class="lineno"> 1571</span></div>
<div class="line"><a id="l01578" name="l01578"></a><span class="lineno"> 1578</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01579" name="l01579"></a><span class="lineno"> 1579</span>{</div>
<div class="line"><a id="l01580" name="l01580"></a><span class="lineno"> 1580</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c">TIM_CR1_UDIS</a>) == (uint32_t)RESET) ? 1UL : 0UL);</div>
<div class="line"><a id="l01581" name="l01581"></a><span class="lineno"> 1581</span>}</div>
<div class="line"><a id="l01582" name="l01582"></a><span class="lineno"> 1582</span></div>
<div class="line"><a id="l01599" name="l01599"></a><span class="lineno"> 1599</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetUpdateSource(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t UpdateSource)</div>
<div class="line"><a id="l01600" name="l01600"></a><span class="lineno"> 1600</span>{</div>
<div class="line"><a id="l01601" name="l01601"></a><span class="lineno"> 1601</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b">TIM_CR1_URS</a>, UpdateSource);</div>
<div class="line"><a id="l01602" name="l01602"></a><span class="lineno"> 1602</span>}</div>
<div class="line"><a id="l01603" name="l01603"></a><span class="lineno"> 1603</span></div>
<div class="line"><a id="l01612" name="l01612"></a><span class="lineno"> 1612</span>__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01613" name="l01613"></a><span class="lineno"> 1613</span>{</div>
<div class="line"><a id="l01614" name="l01614"></a><span class="lineno"> 1614</span>  <span class="keywordflow">return</span> (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b">TIM_CR1_URS</a>));</div>
<div class="line"><a id="l01615" name="l01615"></a><span class="lineno"> 1615</span>}</div>
<div class="line"><a id="l01616" name="l01616"></a><span class="lineno"> 1616</span></div>
<div class="line"><a id="l01626" name="l01626"></a><span class="lineno"> 1626</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetOnePulseMode(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t OnePulseMode)</div>
<div class="line"><a id="l01627" name="l01627"></a><span class="lineno"> 1627</span>{</div>
<div class="line"><a id="l01628" name="l01628"></a><span class="lineno"> 1628</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6d3d1488296350af6d36fbbf71905d29">TIM_CR1_OPM</a>, OnePulseMode);</div>
<div class="line"><a id="l01629" name="l01629"></a><span class="lineno"> 1629</span>}</div>
<div class="line"><a id="l01630" name="l01630"></a><span class="lineno"> 1630</span></div>
<div class="line"><a id="l01639" name="l01639"></a><span class="lineno"> 1639</span>__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01640" name="l01640"></a><span class="lineno"> 1640</span>{</div>
<div class="line"><a id="l01641" name="l01641"></a><span class="lineno"> 1641</span>  <span class="keywordflow">return</span> (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6d3d1488296350af6d36fbbf71905d29">TIM_CR1_OPM</a>));</div>
<div class="line"><a id="l01642" name="l01642"></a><span class="lineno"> 1642</span>}</div>
<div class="line"><a id="l01643" name="l01643"></a><span class="lineno"> 1643</span></div>
<div class="line"><a id="l01663" name="l01663"></a><span class="lineno"> 1663</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetCounterMode(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CounterMode)</div>
<div class="line"><a id="l01664" name="l01664"></a><span class="lineno"> 1664</span>{</div>
<div class="line"><a id="l01665" name="l01665"></a><span class="lineno"> 1665</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa">TIM_CR1_DIR</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1">TIM_CR1_CMS</a>), CounterMode);</div>
<div class="line"><a id="l01666" name="l01666"></a><span class="lineno"> 1666</span>}</div>
<div class="line"><a id="l01667" name="l01667"></a><span class="lineno"> 1667</span></div>
<div class="line"><a id="l01683" name="l01683"></a><span class="lineno"> 1683</span>__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01684" name="l01684"></a><span class="lineno"> 1684</span>{</div>
<div class="line"><a id="l01685" name="l01685"></a><span class="lineno"> 1685</span>  uint32_t counter_mode;</div>
<div class="line"><a id="l01686" name="l01686"></a><span class="lineno"> 1686</span> </div>
<div class="line"><a id="l01687" name="l01687"></a><span class="lineno"> 1687</span>  counter_mode = (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1">TIM_CR1_CMS</a>));</div>
<div class="line"><a id="l01688" name="l01688"></a><span class="lineno"> 1688</span> </div>
<div class="line"><a id="l01689" name="l01689"></a><span class="lineno"> 1689</span>  <span class="keywordflow">if</span> (counter_mode == 0U)</div>
<div class="line"><a id="l01690" name="l01690"></a><span class="lineno"> 1690</span>  {</div>
<div class="line"><a id="l01691" name="l01691"></a><span class="lineno"> 1691</span>    counter_mode = (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa">TIM_CR1_DIR</a>));</div>
<div class="line"><a id="l01692" name="l01692"></a><span class="lineno"> 1692</span>  }</div>
<div class="line"><a id="l01693" name="l01693"></a><span class="lineno"> 1693</span> </div>
<div class="line"><a id="l01694" name="l01694"></a><span class="lineno"> 1694</span>  <span class="keywordflow">return</span> counter_mode;</div>
<div class="line"><a id="l01695" name="l01695"></a><span class="lineno"> 1695</span>}</div>
<div class="line"><a id="l01696" name="l01696"></a><span class="lineno"> 1696</span></div>
<div class="line"><a id="l01703" name="l01703"></a><span class="lineno"> 1703</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableARRPreload(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01704" name="l01704"></a><span class="lineno"> 1704</span>{</div>
<div class="line"><a id="l01705" name="l01705"></a><span class="lineno"> 1705</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">TIM_CR1_ARPE</a>);</div>
<div class="line"><a id="l01706" name="l01706"></a><span class="lineno"> 1706</span>}</div>
<div class="line"><a id="l01707" name="l01707"></a><span class="lineno"> 1707</span></div>
<div class="line"><a id="l01714" name="l01714"></a><span class="lineno"> 1714</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableARRPreload(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01715" name="l01715"></a><span class="lineno"> 1715</span>{</div>
<div class="line"><a id="l01716" name="l01716"></a><span class="lineno"> 1716</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">TIM_CR1_ARPE</a>);</div>
<div class="line"><a id="l01717" name="l01717"></a><span class="lineno"> 1717</span>}</div>
<div class="line"><a id="l01718" name="l01718"></a><span class="lineno"> 1718</span></div>
<div class="line"><a id="l01725" name="l01725"></a><span class="lineno"> 1725</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01726" name="l01726"></a><span class="lineno"> 1726</span>{</div>
<div class="line"><a id="l01727" name="l01727"></a><span class="lineno"> 1727</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">TIM_CR1_ARPE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">TIM_CR1_ARPE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l01728" name="l01728"></a><span class="lineno"> 1728</span>}</div>
<div class="line"><a id="l01729" name="l01729"></a><span class="lineno"> 1729</span></div>
<div class="line"><a id="l01744" name="l01744"></a><span class="lineno"> 1744</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetClockDivision(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t ClockDivision)</div>
<div class="line"><a id="l01745" name="l01745"></a><span class="lineno"> 1745</span>{</div>
<div class="line"><a id="l01746" name="l01746"></a><span class="lineno"> 1746</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72">TIM_CR1_CKD</a>, ClockDivision);</div>
<div class="line"><a id="l01747" name="l01747"></a><span class="lineno"> 1747</span>}</div>
<div class="line"><a id="l01748" name="l01748"></a><span class="lineno"> 1748</span></div>
<div class="line"><a id="l01762" name="l01762"></a><span class="lineno"> 1762</span>__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01763" name="l01763"></a><span class="lineno"> 1763</span>{</div>
<div class="line"><a id="l01764" name="l01764"></a><span class="lineno"> 1764</span>  <span class="keywordflow">return</span> (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72">TIM_CR1_CKD</a>));</div>
<div class="line"><a id="l01765" name="l01765"></a><span class="lineno"> 1765</span>}</div>
<div class="line"><a id="l01766" name="l01766"></a><span class="lineno"> 1766</span></div>
<div class="line"><a id="l01776" name="l01776"></a><span class="lineno"> 1776</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetCounter(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Counter)</div>
<div class="line"><a id="l01777" name="l01777"></a><span class="lineno"> 1777</span>{</div>
<div class="line"><a id="l01778" name="l01778"></a><span class="lineno"> 1778</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6fdd2a7fb88d28670b472aaac0d9d262">CNT</a>, Counter);</div>
<div class="line"><a id="l01779" name="l01779"></a><span class="lineno"> 1779</span>}</div>
<div class="line"><a id="l01780" name="l01780"></a><span class="lineno"> 1780</span></div>
<div class="line"><a id="l01789" name="l01789"></a><span class="lineno"> 1789</span>__STATIC_INLINE uint32_t LL_TIM_GetCounter(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01790" name="l01790"></a><span class="lineno"> 1790</span>{</div>
<div class="line"><a id="l01791" name="l01791"></a><span class="lineno"> 1791</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6fdd2a7fb88d28670b472aaac0d9d262">CNT</a>));</div>
<div class="line"><a id="l01792" name="l01792"></a><span class="lineno"> 1792</span>}</div>
<div class="line"><a id="l01793" name="l01793"></a><span class="lineno"> 1793</span></div>
<div class="line"><a id="l01802" name="l01802"></a><span class="lineno"> 1802</span>__STATIC_INLINE uint32_t LL_TIM_GetDirection(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01803" name="l01803"></a><span class="lineno"> 1803</span>{</div>
<div class="line"><a id="l01804" name="l01804"></a><span class="lineno"> 1804</span>  <span class="keywordflow">return</span> (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa">TIM_CR1_DIR</a>));</div>
<div class="line"><a id="l01805" name="l01805"></a><span class="lineno"> 1805</span>}</div>
<div class="line"><a id="l01806" name="l01806"></a><span class="lineno"> 1806</span></div>
<div class="line"><a id="l01818" name="l01818"></a><span class="lineno"> 1818</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetPrescaler(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Prescaler)</div>
<div class="line"><a id="l01819" name="l01819"></a><span class="lineno"> 1819</span>{</div>
<div class="line"><a id="l01820" name="l01820"></a><span class="lineno"> 1820</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad03c852f58077a11e75f8af42fa6d921">PSC</a>, Prescaler);</div>
<div class="line"><a id="l01821" name="l01821"></a><span class="lineno"> 1821</span>}</div>
<div class="line"><a id="l01822" name="l01822"></a><span class="lineno"> 1822</span></div>
<div class="line"><a id="l01829" name="l01829"></a><span class="lineno"> 1829</span>__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01830" name="l01830"></a><span class="lineno"> 1830</span>{</div>
<div class="line"><a id="l01831" name="l01831"></a><span class="lineno"> 1831</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad03c852f58077a11e75f8af42fa6d921">PSC</a>));</div>
<div class="line"><a id="l01832" name="l01832"></a><span class="lineno"> 1832</span>}</div>
<div class="line"><a id="l01833" name="l01833"></a><span class="lineno"> 1833</span></div>
<div class="line"><a id="l01845" name="l01845"></a><span class="lineno"> 1845</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetAutoReload(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t AutoReload)</div>
<div class="line"><a id="l01846" name="l01846"></a><span class="lineno"> 1846</span>{</div>
<div class="line"><a id="l01847" name="l01847"></a><span class="lineno"> 1847</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6a42766a6ca3c7fe10a810ebd6b9d627">ARR</a>, AutoReload);</div>
<div class="line"><a id="l01848" name="l01848"></a><span class="lineno"> 1848</span>}</div>
<div class="line"><a id="l01849" name="l01849"></a><span class="lineno"> 1849</span></div>
<div class="line"><a id="l01858" name="l01858"></a><span class="lineno"> 1858</span>__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01859" name="l01859"></a><span class="lineno"> 1859</span>{</div>
<div class="line"><a id="l01860" name="l01860"></a><span class="lineno"> 1860</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6a42766a6ca3c7fe10a810ebd6b9d627">ARR</a>));</div>
<div class="line"><a id="l01861" name="l01861"></a><span class="lineno"> 1861</span>}</div>
<div class="line"><a id="l01862" name="l01862"></a><span class="lineno"> 1862</span></div>
<div class="line"><a id="l01873" name="l01873"></a><span class="lineno"> 1873</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetRepetitionCounter(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t RepetitionCounter)</div>
<div class="line"><a id="l01874" name="l01874"></a><span class="lineno"> 1874</span>{</div>
<div class="line"><a id="l01875" name="l01875"></a><span class="lineno"> 1875</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad432e2a315abf68e6c295fb4ebc37534">RCR</a>, RepetitionCounter);</div>
<div class="line"><a id="l01876" name="l01876"></a><span class="lineno"> 1876</span>}</div>
<div class="line"><a id="l01877" name="l01877"></a><span class="lineno"> 1877</span></div>
<div class="line"><a id="l01886" name="l01886"></a><span class="lineno"> 1886</span>__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01887" name="l01887"></a><span class="lineno"> 1887</span>{</div>
<div class="line"><a id="l01888" name="l01888"></a><span class="lineno"> 1888</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad432e2a315abf68e6c295fb4ebc37534">RCR</a>));</div>
<div class="line"><a id="l01889" name="l01889"></a><span class="lineno"> 1889</span>}</div>
<div class="line"><a id="l01890" name="l01890"></a><span class="lineno"> 1890</span></div>
<div class="line"><a id="l01899" name="l01899"></a><span class="lineno"> 1899</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableUIFRemap(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01900" name="l01900"></a><span class="lineno"> 1900</span>{</div>
<div class="line"><a id="l01901" name="l01901"></a><span class="lineno"> 1901</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf0c8b29f2a8d1426cf31270643d811c7">TIM_CR1_UIFREMAP</a>);</div>
<div class="line"><a id="l01902" name="l01902"></a><span class="lineno"> 1902</span>}</div>
<div class="line"><a id="l01903" name="l01903"></a><span class="lineno"> 1903</span></div>
<div class="line"><a id="l01910" name="l01910"></a><span class="lineno"> 1910</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableUIFRemap(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01911" name="l01911"></a><span class="lineno"> 1911</span>{</div>
<div class="line"><a id="l01912" name="l01912"></a><span class="lineno"> 1912</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">CR1</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf0c8b29f2a8d1426cf31270643d811c7">TIM_CR1_UIFREMAP</a>);</div>
<div class="line"><a id="l01913" name="l01913"></a><span class="lineno"> 1913</span>}</div>
<div class="line"><a id="l01914" name="l01914"></a><span class="lineno"> 1914</span></div>
<div class="line"><a id="l01920" name="l01920"></a><span class="lineno"> 1920</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(<span class="keyword">const</span> uint32_t Counter)</div>
<div class="line"><a id="l01921" name="l01921"></a><span class="lineno"> 1921</span>{</div>
<div class="line"><a id="l01922" name="l01922"></a><span class="lineno"> 1922</span>  <span class="keywordflow">return</span> (((Counter &amp; <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga9060f1ca4c5df1ab6e70af699ac71a16">TIM_CNT_UIFCPY</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga9060f1ca4c5df1ab6e70af699ac71a16">TIM_CNT_UIFCPY</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l01923" name="l01923"></a><span class="lineno"> 1923</span>}</div>
<div class="line"><a id="l01924" name="l01924"></a><span class="lineno"> 1924</span></div>
<div class="line"><a id="l01928" name="l01928"></a><span class="lineno"> 1928</span></div>
<div class="line"><a id="l01943" name="l01943"></a><span class="lineno"> 1943</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_CC_EnablePreload(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01944" name="l01944"></a><span class="lineno"> 1944</span>{</div>
<div class="line"><a id="l01945" name="l01945"></a><span class="lineno"> 1945</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">TIM_CR2_CCPC</a>);</div>
<div class="line"><a id="l01946" name="l01946"></a><span class="lineno"> 1946</span>}</div>
<div class="line"><a id="l01947" name="l01947"></a><span class="lineno"> 1947</span></div>
<div class="line"><a id="l01956" name="l01956"></a><span class="lineno"> 1956</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_CC_DisablePreload(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01957" name="l01957"></a><span class="lineno"> 1957</span>{</div>
<div class="line"><a id="l01958" name="l01958"></a><span class="lineno"> 1958</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">TIM_CR2_CCPC</a>);</div>
<div class="line"><a id="l01959" name="l01959"></a><span class="lineno"> 1959</span>}</div>
<div class="line"><a id="l01960" name="l01960"></a><span class="lineno"> 1960</span></div>
<div class="line"><a id="l01967" name="l01967"></a><span class="lineno"> 1967</span>__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l01968" name="l01968"></a><span class="lineno"> 1968</span>{</div>
<div class="line"><a id="l01969" name="l01969"></a><span class="lineno"> 1969</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">TIM_CR2_CCPC</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">TIM_CR2_CCPC</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l01970" name="l01970"></a><span class="lineno"> 1970</span>}</div>
<div class="line"><a id="l01971" name="l01971"></a><span class="lineno"> 1971</span></div>
<div class="line"><a id="l01983" name="l01983"></a><span class="lineno"> 1983</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_CC_SetUpdate(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CCUpdateSource)</div>
<div class="line"><a id="l01984" name="l01984"></a><span class="lineno"> 1984</span>{</div>
<div class="line"><a id="l01985" name="l01985"></a><span class="lineno"> 1985</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf0328c1339b2b1633ef7a8db4c02d0d5">TIM_CR2_CCUS</a>, CCUpdateSource);</div>
<div class="line"><a id="l01986" name="l01986"></a><span class="lineno"> 1986</span>}</div>
<div class="line"><a id="l01987" name="l01987"></a><span class="lineno"> 1987</span></div>
<div class="line"><a id="l01997" name="l01997"></a><span class="lineno"> 1997</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_CC_SetDMAReqTrigger(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t DMAReqTrigger)</div>
<div class="line"><a id="l01998" name="l01998"></a><span class="lineno"> 1998</span>{</div>
<div class="line"><a id="l01999" name="l01999"></a><span class="lineno"> 1999</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e">TIM_CR2_CCDS</a>, DMAReqTrigger);</div>
<div class="line"><a id="l02000" name="l02000"></a><span class="lineno"> 2000</span>}</div>
<div class="line"><a id="l02001" name="l02001"></a><span class="lineno"> 2001</span></div>
<div class="line"><a id="l02010" name="l02010"></a><span class="lineno"> 2010</span>__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l02011" name="l02011"></a><span class="lineno"> 2011</span>{</div>
<div class="line"><a id="l02012" name="l02012"></a><span class="lineno"> 2012</span>  <span class="keywordflow">return</span> (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e">TIM_CR2_CCDS</a>));</div>
<div class="line"><a id="l02013" name="l02013"></a><span class="lineno"> 2013</span>}</div>
<div class="line"><a id="l02014" name="l02014"></a><span class="lineno"> 2014</span></div>
<div class="line"><a id="l02029" name="l02029"></a><span class="lineno"> 2029</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_CC_SetLockLevel(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t LockLevel)</div>
<div class="line"><a id="l02030" name="l02030"></a><span class="lineno"> 2030</span>{</div>
<div class="line"><a id="l02031" name="l02031"></a><span class="lineno"> 2031</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7e4215d17f0548dfcf0b15fe4d0f4651">TIM_BDTR_LOCK</a>, LockLevel);</div>
<div class="line"><a id="l02032" name="l02032"></a><span class="lineno"> 2032</span>}</div>
<div class="line"><a id="l02033" name="l02033"></a><span class="lineno"> 2033</span></div>
<div class="line"><a id="l02058" name="l02058"></a><span class="lineno"> 2058</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_CC_EnableChannel(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channels)</div>
<div class="line"><a id="l02059" name="l02059"></a><span class="lineno"> 2059</span>{</div>
<div class="line"><a id="l02060" name="l02060"></a><span class="lineno"> 2060</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, Channels);</div>
<div class="line"><a id="l02061" name="l02061"></a><span class="lineno"> 2061</span>}</div>
<div class="line"><a id="l02062" name="l02062"></a><span class="lineno"> 2062</span></div>
<div class="line"><a id="l02087" name="l02087"></a><span class="lineno"> 2087</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_CC_DisableChannel(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channels)</div>
<div class="line"><a id="l02088" name="l02088"></a><span class="lineno"> 2088</span>{</div>
<div class="line"><a id="l02089" name="l02089"></a><span class="lineno"> 2089</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, Channels);</div>
<div class="line"><a id="l02090" name="l02090"></a><span class="lineno"> 2090</span>}</div>
<div class="line"><a id="l02091" name="l02091"></a><span class="lineno"> 2091</span></div>
<div class="line"><a id="l02116" name="l02116"></a><span class="lineno"> 2116</span>__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channels)</div>
<div class="line"><a id="l02117" name="l02117"></a><span class="lineno"> 2117</span>{</div>
<div class="line"><a id="l02118" name="l02118"></a><span class="lineno"> 2118</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, Channels) == (Channels)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02119" name="l02119"></a><span class="lineno"> 2119</span>}</div>
<div class="line"><a id="l02120" name="l02120"></a><span class="lineno"> 2120</span></div>
<div class="line"><a id="l02124" name="l02124"></a><span class="lineno"> 2124</span></div>
<div class="line"><a id="l02161" name="l02161"></a><span class="lineno"> 2161</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_ConfigOutput(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t Configuration)</div>
<div class="line"><a id="l02162" name="l02162"></a><span class="lineno"> 2162</span>{</div>
<div class="line"><a id="l02163" name="l02163"></a><span class="lineno"> 2163</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02164" name="l02164"></a><span class="lineno"> 2164</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02165" name="l02165"></a><span class="lineno"> 2165</span>  CLEAR_BIT(*pReg, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel]));</div>
<div class="line"><a id="l02166" name="l02166"></a><span class="lineno"> 2166</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a> &lt;&lt; SHIFT_TAB_CCxP[iChannel]),</div>
<div class="line"><a id="l02167" name="l02167"></a><span class="lineno"> 2167</span>             (Configuration &amp; <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a>) &lt;&lt; SHIFT_TAB_CCxP[iChannel]);</div>
<div class="line"><a id="l02168" name="l02168"></a><span class="lineno"> 2168</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">TIM_CR2_OIS1</a> &lt;&lt; SHIFT_TAB_OISx[iChannel]),</div>
<div class="line"><a id="l02169" name="l02169"></a><span class="lineno"> 2169</span>             (Configuration &amp; <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">TIM_CR2_OIS1</a>) &lt;&lt; SHIFT_TAB_OISx[iChannel]);</div>
<div class="line"><a id="l02170" name="l02170"></a><span class="lineno"> 2170</span>}</div>
<div class="line"><a id="l02171" name="l02171"></a><span class="lineno"> 2171</span></div>
<div class="line"><a id="l02206" name="l02206"></a><span class="lineno"> 2206</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetMode(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t Mode)</div>
<div class="line"><a id="l02207" name="l02207"></a><span class="lineno"> 2207</span>{</div>
<div class="line"><a id="l02208" name="l02208"></a><span class="lineno"> 2208</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02209" name="l02209"></a><span class="lineno"> 2209</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02210" name="l02210"></a><span class="lineno"> 2210</span>  MODIFY_REG(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">TIM_CCMR1_OC1M</a>  | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a>) &lt;&lt; SHIFT_TAB_OCxx[iChannel]), Mode &lt;&lt; SHIFT_TAB_OCxx[iChannel]);</div>
<div class="line"><a id="l02211" name="l02211"></a><span class="lineno"> 2211</span>}</div>
<div class="line"><a id="l02212" name="l02212"></a><span class="lineno"> 2212</span></div>
<div class="line"><a id="l02245" name="l02245"></a><span class="lineno"> 2245</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02246" name="l02246"></a><span class="lineno"> 2246</span>{</div>
<div class="line"><a id="l02247" name="l02247"></a><span class="lineno"> 2247</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02248" name="l02248"></a><span class="lineno"> 2248</span>  <span class="keyword">const</span> <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02249" name="l02249"></a><span class="lineno"> 2249</span>  <span class="keywordflow">return</span> (READ_BIT(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">TIM_CCMR1_OC1M</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a>) &lt;&lt; SHIFT_TAB_OCxx[iChannel])) &gt;&gt; SHIFT_TAB_OCxx[iChannel]);</div>
<div class="line"><a id="l02250" name="l02250"></a><span class="lineno"> 2250</span>}</div>
<div class="line"><a id="l02251" name="l02251"></a><span class="lineno"> 2251</span></div>
<div class="line"><a id="l02279" name="l02279"></a><span class="lineno"> 2279</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetPolarity(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t Polarity)</div>
<div class="line"><a id="l02280" name="l02280"></a><span class="lineno"> 2280</span>{</div>
<div class="line"><a id="l02281" name="l02281"></a><span class="lineno"> 2281</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02282" name="l02282"></a><span class="lineno"> 2282</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a> &lt;&lt; SHIFT_TAB_CCxP[iChannel]),  Polarity &lt;&lt; SHIFT_TAB_CCxP[iChannel]);</div>
<div class="line"><a id="l02283" name="l02283"></a><span class="lineno"> 2283</span>}</div>
<div class="line"><a id="l02284" name="l02284"></a><span class="lineno"> 2284</span></div>
<div class="line"><a id="l02311" name="l02311"></a><span class="lineno"> 2311</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02312" name="l02312"></a><span class="lineno"> 2312</span>{</div>
<div class="line"><a id="l02313" name="l02313"></a><span class="lineno"> 2313</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02314" name="l02314"></a><span class="lineno"> 2314</span>  <span class="keywordflow">return</span> (READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a> &lt;&lt; SHIFT_TAB_CCxP[iChannel])) &gt;&gt; SHIFT_TAB_CCxP[iChannel]);</div>
<div class="line"><a id="l02315" name="l02315"></a><span class="lineno"> 2315</span>}</div>
<div class="line"><a id="l02316" name="l02316"></a><span class="lineno"> 2316</span></div>
<div class="line"><a id="l02348" name="l02348"></a><span class="lineno"> 2348</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetIdleState(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t IdleState)</div>
<div class="line"><a id="l02349" name="l02349"></a><span class="lineno"> 2349</span>{</div>
<div class="line"><a id="l02350" name="l02350"></a><span class="lineno"> 2350</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02351" name="l02351"></a><span class="lineno"> 2351</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">TIM_CR2_OIS1</a> &lt;&lt; SHIFT_TAB_OISx[iChannel]),  IdleState &lt;&lt; SHIFT_TAB_OISx[iChannel]);</div>
<div class="line"><a id="l02352" name="l02352"></a><span class="lineno"> 2352</span>}</div>
<div class="line"><a id="l02353" name="l02353"></a><span class="lineno"> 2353</span></div>
<div class="line"><a id="l02380" name="l02380"></a><span class="lineno"> 2380</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02381" name="l02381"></a><span class="lineno"> 2381</span>{</div>
<div class="line"><a id="l02382" name="l02382"></a><span class="lineno"> 2382</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02383" name="l02383"></a><span class="lineno"> 2383</span>  <span class="keywordflow">return</span> (READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">TIM_CR2_OIS1</a> &lt;&lt; SHIFT_TAB_OISx[iChannel])) &gt;&gt; SHIFT_TAB_OISx[iChannel]);</div>
<div class="line"><a id="l02384" name="l02384"></a><span class="lineno"> 2384</span>}</div>
<div class="line"><a id="l02385" name="l02385"></a><span class="lineno"> 2385</span></div>
<div class="line"><a id="l02405" name="l02405"></a><span class="lineno"> 2405</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_EnableFast(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02406" name="l02406"></a><span class="lineno"> 2406</span>{</div>
<div class="line"><a id="l02407" name="l02407"></a><span class="lineno"> 2407</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02408" name="l02408"></a><span class="lineno"> 2408</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02409" name="l02409"></a><span class="lineno"> 2409</span>  SET_BIT(*pReg, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e">TIM_CCMR1_OC1FE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel]));</div>
<div class="line"><a id="l02410" name="l02410"></a><span class="lineno"> 2410</span> </div>
<div class="line"><a id="l02411" name="l02411"></a><span class="lineno"> 2411</span>}</div>
<div class="line"><a id="l02412" name="l02412"></a><span class="lineno"> 2412</span></div>
<div class="line"><a id="l02431" name="l02431"></a><span class="lineno"> 2431</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_DisableFast(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02432" name="l02432"></a><span class="lineno"> 2432</span>{</div>
<div class="line"><a id="l02433" name="l02433"></a><span class="lineno"> 2433</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02434" name="l02434"></a><span class="lineno"> 2434</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02435" name="l02435"></a><span class="lineno"> 2435</span>  CLEAR_BIT(*pReg, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e">TIM_CCMR1_OC1FE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel]));</div>
<div class="line"><a id="l02436" name="l02436"></a><span class="lineno"> 2436</span> </div>
<div class="line"><a id="l02437" name="l02437"></a><span class="lineno"> 2437</span>}</div>
<div class="line"><a id="l02438" name="l02438"></a><span class="lineno"> 2438</span></div>
<div class="line"><a id="l02457" name="l02457"></a><span class="lineno"> 2457</span>__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02458" name="l02458"></a><span class="lineno"> 2458</span>{</div>
<div class="line"><a id="l02459" name="l02459"></a><span class="lineno"> 2459</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02460" name="l02460"></a><span class="lineno"> 2460</span>  <span class="keyword">const</span> <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02461" name="l02461"></a><span class="lineno"> 2461</span>  uint32_t bitfield = <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e">TIM_CCMR1_OC1FE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel];</div>
<div class="line"><a id="l02462" name="l02462"></a><span class="lineno"> 2462</span>  <span class="keywordflow">return</span> ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);</div>
<div class="line"><a id="l02463" name="l02463"></a><span class="lineno"> 2463</span>}</div>
<div class="line"><a id="l02464" name="l02464"></a><span class="lineno"> 2464</span></div>
<div class="line"><a id="l02483" name="l02483"></a><span class="lineno"> 2483</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_EnablePreload(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02484" name="l02484"></a><span class="lineno"> 2484</span>{</div>
<div class="line"><a id="l02485" name="l02485"></a><span class="lineno"> 2485</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02486" name="l02486"></a><span class="lineno"> 2486</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02487" name="l02487"></a><span class="lineno"> 2487</span>  SET_BIT(*pReg, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb">TIM_CCMR1_OC1PE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel]));</div>
<div class="line"><a id="l02488" name="l02488"></a><span class="lineno"> 2488</span>}</div>
<div class="line"><a id="l02489" name="l02489"></a><span class="lineno"> 2489</span></div>
<div class="line"><a id="l02508" name="l02508"></a><span class="lineno"> 2508</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_DisablePreload(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02509" name="l02509"></a><span class="lineno"> 2509</span>{</div>
<div class="line"><a id="l02510" name="l02510"></a><span class="lineno"> 2510</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02511" name="l02511"></a><span class="lineno"> 2511</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02512" name="l02512"></a><span class="lineno"> 2512</span>  CLEAR_BIT(*pReg, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb">TIM_CCMR1_OC1PE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel]));</div>
<div class="line"><a id="l02513" name="l02513"></a><span class="lineno"> 2513</span>}</div>
<div class="line"><a id="l02514" name="l02514"></a><span class="lineno"> 2514</span></div>
<div class="line"><a id="l02533" name="l02533"></a><span class="lineno"> 2533</span>__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02534" name="l02534"></a><span class="lineno"> 2534</span>{</div>
<div class="line"><a id="l02535" name="l02535"></a><span class="lineno"> 2535</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02536" name="l02536"></a><span class="lineno"> 2536</span>  <span class="keyword">const</span> <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02537" name="l02537"></a><span class="lineno"> 2537</span>  uint32_t bitfield = <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb">TIM_CCMR1_OC1PE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel];</div>
<div class="line"><a id="l02538" name="l02538"></a><span class="lineno"> 2538</span>  <span class="keywordflow">return</span> ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);</div>
<div class="line"><a id="l02539" name="l02539"></a><span class="lineno"> 2539</span>}</div>
<div class="line"><a id="l02540" name="l02540"></a><span class="lineno"> 2540</span></div>
<div class="line"><a id="l02562" name="l02562"></a><span class="lineno"> 2562</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_EnableClear(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02563" name="l02563"></a><span class="lineno"> 2563</span>{</div>
<div class="line"><a id="l02564" name="l02564"></a><span class="lineno"> 2564</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02565" name="l02565"></a><span class="lineno"> 2565</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02566" name="l02566"></a><span class="lineno"> 2566</span>  SET_BIT(*pReg, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba">TIM_CCMR1_OC1CE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel]));</div>
<div class="line"><a id="l02567" name="l02567"></a><span class="lineno"> 2567</span>}</div>
<div class="line"><a id="l02568" name="l02568"></a><span class="lineno"> 2568</span></div>
<div class="line"><a id="l02589" name="l02589"></a><span class="lineno"> 2589</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_DisableClear(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02590" name="l02590"></a><span class="lineno"> 2590</span>{</div>
<div class="line"><a id="l02591" name="l02591"></a><span class="lineno"> 2591</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02592" name="l02592"></a><span class="lineno"> 2592</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02593" name="l02593"></a><span class="lineno"> 2593</span>  CLEAR_BIT(*pReg, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba">TIM_CCMR1_OC1CE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel]));</div>
<div class="line"><a id="l02594" name="l02594"></a><span class="lineno"> 2594</span>}</div>
<div class="line"><a id="l02595" name="l02595"></a><span class="lineno"> 2595</span></div>
<div class="line"><a id="l02618" name="l02618"></a><span class="lineno"> 2618</span>__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02619" name="l02619"></a><span class="lineno"> 2619</span>{</div>
<div class="line"><a id="l02620" name="l02620"></a><span class="lineno"> 2620</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02621" name="l02621"></a><span class="lineno"> 2621</span>  <span class="keyword">const</span> <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02622" name="l02622"></a><span class="lineno"> 2622</span>  uint32_t bitfield = <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba">TIM_CCMR1_OC1CE</a> &lt;&lt; SHIFT_TAB_OCxx[iChannel];</div>
<div class="line"><a id="l02623" name="l02623"></a><span class="lineno"> 2623</span>  <span class="keywordflow">return</span> ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);</div>
<div class="line"><a id="l02624" name="l02624"></a><span class="lineno"> 2624</span>}</div>
<div class="line"><a id="l02625" name="l02625"></a><span class="lineno"> 2625</span></div>
<div class="line"><a id="l02637" name="l02637"></a><span class="lineno"> 2637</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetDeadTime(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t DeadTime)</div>
<div class="line"><a id="l02638" name="l02638"></a><span class="lineno"> 2638</span>{</div>
<div class="line"><a id="l02639" name="l02639"></a><span class="lineno"> 2639</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gabcf985e9c78f15e1e44b2bc4d2bafc67">TIM_BDTR_DTG</a>, DeadTime);</div>
<div class="line"><a id="l02640" name="l02640"></a><span class="lineno"> 2640</span>}</div>
<div class="line"><a id="l02641" name="l02641"></a><span class="lineno"> 2641</span></div>
<div class="line"><a id="l02654" name="l02654"></a><span class="lineno"> 2654</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetCompareCH1(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CompareValue)</div>
<div class="line"><a id="l02655" name="l02655"></a><span class="lineno"> 2655</span>{</div>
<div class="line"><a id="l02656" name="l02656"></a><span class="lineno"> 2656</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0dd9c06729a5eb6179c6d0d60faca7ed">CCR1</a>, CompareValue);</div>
<div class="line"><a id="l02657" name="l02657"></a><span class="lineno"> 2657</span>}</div>
<div class="line"><a id="l02658" name="l02658"></a><span class="lineno"> 2658</span></div>
<div class="line"><a id="l02671" name="l02671"></a><span class="lineno"> 2671</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetCompareCH2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CompareValue)</div>
<div class="line"><a id="l02672" name="l02672"></a><span class="lineno"> 2672</span>{</div>
<div class="line"><a id="l02673" name="l02673"></a><span class="lineno"> 2673</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a4d1171e9a61538424b8ef1f2571986d0">CCR2</a>, CompareValue);</div>
<div class="line"><a id="l02674" name="l02674"></a><span class="lineno"> 2674</span>}</div>
<div class="line"><a id="l02675" name="l02675"></a><span class="lineno"> 2675</span></div>
<div class="line"><a id="l02688" name="l02688"></a><span class="lineno"> 2688</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetCompareCH3(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CompareValue)</div>
<div class="line"><a id="l02689" name="l02689"></a><span class="lineno"> 2689</span>{</div>
<div class="line"><a id="l02690" name="l02690"></a><span class="lineno"> 2690</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ac83441bfb8d0287080dcbd945a272a74">CCR3</a>, CompareValue);</div>
<div class="line"><a id="l02691" name="l02691"></a><span class="lineno"> 2691</span>}</div>
<div class="line"><a id="l02692" name="l02692"></a><span class="lineno"> 2692</span></div>
<div class="line"><a id="l02705" name="l02705"></a><span class="lineno"> 2705</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetCompareCH4(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CompareValue)</div>
<div class="line"><a id="l02706" name="l02706"></a><span class="lineno"> 2706</span>{</div>
<div class="line"><a id="l02707" name="l02707"></a><span class="lineno"> 2707</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a5ba381c3f312fdf5e0b4119641b3b0aa">CCR4</a>, CompareValue);</div>
<div class="line"><a id="l02708" name="l02708"></a><span class="lineno"> 2708</span>}</div>
<div class="line"><a id="l02709" name="l02709"></a><span class="lineno"> 2709</span></div>
<div class="line"><a id="l02719" name="l02719"></a><span class="lineno"> 2719</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetCompareCH5(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CompareValue)</div>
<div class="line"><a id="l02720" name="l02720"></a><span class="lineno"> 2720</span>{</div>
<div class="line"><a id="l02721" name="l02721"></a><span class="lineno"> 2721</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#af30dc563e6c1b7b7e01e393feb484080">CCR5</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga57a4e24f3276f4c908874940657dc7e7">TIM_CCR5_CCR5</a>, CompareValue);</div>
<div class="line"><a id="l02722" name="l02722"></a><span class="lineno"> 2722</span>}</div>
<div class="line"><a id="l02723" name="l02723"></a><span class="lineno"> 2723</span></div>
<div class="line"><a id="l02733" name="l02733"></a><span class="lineno"> 2733</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_OC_SetCompareCH6(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t CompareValue)</div>
<div class="line"><a id="l02734" name="l02734"></a><span class="lineno"> 2734</span>{</div>
<div class="line"><a id="l02735" name="l02735"></a><span class="lineno"> 2735</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a374f851b5f1097a3ebd3f494ded6512a">CCR6</a>, CompareValue);</div>
<div class="line"><a id="l02736" name="l02736"></a><span class="lineno"> 2736</span>}</div>
<div class="line"><a id="l02737" name="l02737"></a><span class="lineno"> 2737</span></div>
<div class="line"><a id="l02749" name="l02749"></a><span class="lineno"> 2749</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l02750" name="l02750"></a><span class="lineno"> 2750</span>{</div>
<div class="line"><a id="l02751" name="l02751"></a><span class="lineno"> 2751</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0dd9c06729a5eb6179c6d0d60faca7ed">CCR1</a>));</div>
<div class="line"><a id="l02752" name="l02752"></a><span class="lineno"> 2752</span>}</div>
<div class="line"><a id="l02753" name="l02753"></a><span class="lineno"> 2753</span></div>
<div class="line"><a id="l02765" name="l02765"></a><span class="lineno"> 2765</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l02766" name="l02766"></a><span class="lineno"> 2766</span>{</div>
<div class="line"><a id="l02767" name="l02767"></a><span class="lineno"> 2767</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a4d1171e9a61538424b8ef1f2571986d0">CCR2</a>));</div>
<div class="line"><a id="l02768" name="l02768"></a><span class="lineno"> 2768</span>}</div>
<div class="line"><a id="l02769" name="l02769"></a><span class="lineno"> 2769</span></div>
<div class="line"><a id="l02781" name="l02781"></a><span class="lineno"> 2781</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l02782" name="l02782"></a><span class="lineno"> 2782</span>{</div>
<div class="line"><a id="l02783" name="l02783"></a><span class="lineno"> 2783</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ac83441bfb8d0287080dcbd945a272a74">CCR3</a>));</div>
<div class="line"><a id="l02784" name="l02784"></a><span class="lineno"> 2784</span>}</div>
<div class="line"><a id="l02785" name="l02785"></a><span class="lineno"> 2785</span></div>
<div class="line"><a id="l02797" name="l02797"></a><span class="lineno"> 2797</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l02798" name="l02798"></a><span class="lineno"> 2798</span>{</div>
<div class="line"><a id="l02799" name="l02799"></a><span class="lineno"> 2799</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a5ba381c3f312fdf5e0b4119641b3b0aa">CCR4</a>));</div>
<div class="line"><a id="l02800" name="l02800"></a><span class="lineno"> 2800</span>}</div>
<div class="line"><a id="l02801" name="l02801"></a><span class="lineno"> 2801</span></div>
<div class="line"><a id="l02810" name="l02810"></a><span class="lineno"> 2810</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l02811" name="l02811"></a><span class="lineno"> 2811</span>{</div>
<div class="line"><a id="l02812" name="l02812"></a><span class="lineno"> 2812</span>  <span class="keywordflow">return</span> (uint32_t)(READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#af30dc563e6c1b7b7e01e393feb484080">CCR5</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga57a4e24f3276f4c908874940657dc7e7">TIM_CCR5_CCR5</a>));</div>
<div class="line"><a id="l02813" name="l02813"></a><span class="lineno"> 2813</span>}</div>
<div class="line"><a id="l02814" name="l02814"></a><span class="lineno"> 2814</span></div>
<div class="line"><a id="l02823" name="l02823"></a><span class="lineno"> 2823</span>__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l02824" name="l02824"></a><span class="lineno"> 2824</span>{</div>
<div class="line"><a id="l02825" name="l02825"></a><span class="lineno"> 2825</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a374f851b5f1097a3ebd3f494ded6512a">CCR6</a>));</div>
<div class="line"><a id="l02826" name="l02826"></a><span class="lineno"> 2826</span>}</div>
<div class="line"><a id="l02827" name="l02827"></a><span class="lineno"> 2827</span></div>
<div class="line"><a id="l02843" name="l02843"></a><span class="lineno"> 2843</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetCH5CombinedChannels(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t GroupCH5)</div>
<div class="line"><a id="l02844" name="l02844"></a><span class="lineno"> 2844</span>{</div>
<div class="line"><a id="l02845" name="l02845"></a><span class="lineno"> 2845</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#af30dc563e6c1b7b7e01e393feb484080">CCR5</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaaaf84ef0edc60a2bb1d724fd28ae522e">TIM_CCR5_GC5C3</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga66b51c31aab6f353303cffb10593a027">TIM_CCR5_GC5C2</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadce130a8f74c02de0f6e2f8cb0f16b6e">TIM_CCR5_GC5C1</a>), GroupCH5);</div>
<div class="line"><a id="l02846" name="l02846"></a><span class="lineno"> 2846</span>}</div>
<div class="line"><a id="l02847" name="l02847"></a><span class="lineno"> 2847</span></div>
<div class="line"><a id="l02851" name="l02851"></a><span class="lineno"> 2851</span></div>
<div class="line"><a id="l02890" name="l02890"></a><span class="lineno"> 2890</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_IC_Config(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t Configuration)</div>
<div class="line"><a id="l02891" name="l02891"></a><span class="lineno"> 2891</span>{</div>
<div class="line"><a id="l02892" name="l02892"></a><span class="lineno"> 2892</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02893" name="l02893"></a><span class="lineno"> 2893</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02894" name="l02894"></a><span class="lineno"> 2894</span>  MODIFY_REG(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">TIM_CCMR1_IC1F</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">TIM_CCMR1_IC1PSC</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a>) &lt;&lt; SHIFT_TAB_ICxx[iChannel]),</div>
<div class="line"><a id="l02895" name="l02895"></a><span class="lineno"> 2895</span>             ((Configuration &gt;&gt; 16U) &amp; (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">TIM_CCMR1_IC1F</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">TIM_CCMR1_IC1PSC</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a>))                \</div>
<div class="line"><a id="l02896" name="l02896"></a><span class="lineno"> 2896</span>             &lt;&lt; SHIFT_TAB_ICxx[iChannel]);</div>
<div class="line"><a id="l02897" name="l02897"></a><span class="lineno"> 2897</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">TIM_CCER_CC1NP</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a>) &lt;&lt; SHIFT_TAB_CCxP[iChannel]),</div>
<div class="line"><a id="l02898" name="l02898"></a><span class="lineno"> 2898</span>             (Configuration &amp; (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">TIM_CCER_CC1NP</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a>)) &lt;&lt; SHIFT_TAB_CCxP[iChannel]);</div>
<div class="line"><a id="l02899" name="l02899"></a><span class="lineno"> 2899</span>}</div>
<div class="line"><a id="l02900" name="l02900"></a><span class="lineno"> 2900</span></div>
<div class="line"><a id="l02919" name="l02919"></a><span class="lineno"> 2919</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_IC_SetActiveInput(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t ICActiveInput)</div>
<div class="line"><a id="l02920" name="l02920"></a><span class="lineno"> 2920</span>{</div>
<div class="line"><a id="l02921" name="l02921"></a><span class="lineno"> 2921</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02922" name="l02922"></a><span class="lineno"> 2922</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02923" name="l02923"></a><span class="lineno"> 2923</span>  MODIFY_REG(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a>) &lt;&lt; SHIFT_TAB_ICxx[iChannel]), (ICActiveInput &gt;&gt; 16U) &lt;&lt; SHIFT_TAB_ICxx[iChannel]);</div>
<div class="line"><a id="l02924" name="l02924"></a><span class="lineno"> 2924</span>}</div>
<div class="line"><a id="l02925" name="l02925"></a><span class="lineno"> 2925</span></div>
<div class="line"><a id="l02943" name="l02943"></a><span class="lineno"> 2943</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02944" name="l02944"></a><span class="lineno"> 2944</span>{</div>
<div class="line"><a id="l02945" name="l02945"></a><span class="lineno"> 2945</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02946" name="l02946"></a><span class="lineno"> 2946</span>  <span class="keyword">const</span> <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02947" name="l02947"></a><span class="lineno"> 2947</span>  <span class="keywordflow">return</span> ((READ_BIT(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a>) &lt;&lt; SHIFT_TAB_ICxx[iChannel])) &gt;&gt; SHIFT_TAB_ICxx[iChannel]) &lt;&lt; 16U);</div>
<div class="line"><a id="l02948" name="l02948"></a><span class="lineno"> 2948</span>}</div>
<div class="line"><a id="l02949" name="l02949"></a><span class="lineno"> 2949</span></div>
<div class="line"><a id="l02969" name="l02969"></a><span class="lineno"> 2969</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_IC_SetPrescaler(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t ICPrescaler)</div>
<div class="line"><a id="l02970" name="l02970"></a><span class="lineno"> 2970</span>{</div>
<div class="line"><a id="l02971" name="l02971"></a><span class="lineno"> 2971</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02972" name="l02972"></a><span class="lineno"> 2972</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02973" name="l02973"></a><span class="lineno"> 2973</span>  MODIFY_REG(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">TIM_CCMR1_IC1PSC</a>) &lt;&lt; SHIFT_TAB_ICxx[iChannel]), (ICPrescaler &gt;&gt; 16U) &lt;&lt; SHIFT_TAB_ICxx[iChannel]);</div>
<div class="line"><a id="l02974" name="l02974"></a><span class="lineno"> 2974</span>}</div>
<div class="line"><a id="l02975" name="l02975"></a><span class="lineno"> 2975</span></div>
<div class="line"><a id="l02994" name="l02994"></a><span class="lineno"> 2994</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l02995" name="l02995"></a><span class="lineno"> 2995</span>{</div>
<div class="line"><a id="l02996" name="l02996"></a><span class="lineno"> 2996</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l02997" name="l02997"></a><span class="lineno"> 2997</span>  <span class="keyword">const</span> <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l02998" name="l02998"></a><span class="lineno"> 2998</span>  <span class="keywordflow">return</span> ((READ_BIT(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">TIM_CCMR1_IC1PSC</a>) &lt;&lt; SHIFT_TAB_ICxx[iChannel])) &gt;&gt; SHIFT_TAB_ICxx[iChannel]) &lt;&lt; 16U);</div>
<div class="line"><a id="l02999" name="l02999"></a><span class="lineno"> 2999</span>}</div>
<div class="line"><a id="l03000" name="l03000"></a><span class="lineno"> 3000</span></div>
<div class="line"><a id="l03032" name="l03032"></a><span class="lineno"> 3032</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_IC_SetFilter(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t ICFilter)</div>
<div class="line"><a id="l03033" name="l03033"></a><span class="lineno"> 3033</span>{</div>
<div class="line"><a id="l03034" name="l03034"></a><span class="lineno"> 3034</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l03035" name="l03035"></a><span class="lineno"> 3035</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l03036" name="l03036"></a><span class="lineno"> 3036</span>  MODIFY_REG(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">TIM_CCMR1_IC1F</a>) &lt;&lt; SHIFT_TAB_ICxx[iChannel]), (ICFilter &gt;&gt; 16U) &lt;&lt; SHIFT_TAB_ICxx[iChannel]);</div>
<div class="line"><a id="l03037" name="l03037"></a><span class="lineno"> 3037</span>}</div>
<div class="line"><a id="l03038" name="l03038"></a><span class="lineno"> 3038</span></div>
<div class="line"><a id="l03069" name="l03069"></a><span class="lineno"> 3069</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l03070" name="l03070"></a><span class="lineno"> 3070</span>{</div>
<div class="line"><a id="l03071" name="l03071"></a><span class="lineno"> 3071</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l03072" name="l03072"></a><span class="lineno"> 3072</span>  <span class="keyword">const</span> <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">CCMR1</a>) + OFFSET_TAB_CCMRx[iChannel]));</div>
<div class="line"><a id="l03073" name="l03073"></a><span class="lineno"> 3073</span>  <span class="keywordflow">return</span> ((READ_BIT(*pReg, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">TIM_CCMR1_IC1F</a>) &lt;&lt; SHIFT_TAB_ICxx[iChannel])) &gt;&gt; SHIFT_TAB_ICxx[iChannel]) &lt;&lt; 16U);</div>
<div class="line"><a id="l03074" name="l03074"></a><span class="lineno"> 3074</span>}</div>
<div class="line"><a id="l03075" name="l03075"></a><span class="lineno"> 3075</span></div>
<div class="line"><a id="l03098" name="l03098"></a><span class="lineno"> 3098</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_IC_SetPolarity(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, uint32_t ICPolarity)</div>
<div class="line"><a id="l03099" name="l03099"></a><span class="lineno"> 3099</span>{</div>
<div class="line"><a id="l03100" name="l03100"></a><span class="lineno"> 3100</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l03101" name="l03101"></a><span class="lineno"> 3101</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">TIM_CCER_CC1NP</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a>) &lt;&lt; SHIFT_TAB_CCxP[iChannel]),</div>
<div class="line"><a id="l03102" name="l03102"></a><span class="lineno"> 3102</span>             ICPolarity &lt;&lt; SHIFT_TAB_CCxP[iChannel]);</div>
<div class="line"><a id="l03103" name="l03103"></a><span class="lineno"> 3103</span>}</div>
<div class="line"><a id="l03104" name="l03104"></a><span class="lineno"> 3104</span></div>
<div class="line"><a id="l03126" name="l03126"></a><span class="lineno"> 3126</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel)</div>
<div class="line"><a id="l03127" name="l03127"></a><span class="lineno"> 3127</span>{</div>
<div class="line"><a id="l03128" name="l03128"></a><span class="lineno"> 3128</span>  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);</div>
<div class="line"><a id="l03129" name="l03129"></a><span class="lineno"> 3129</span>  <span class="keywordflow">return</span> (READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">CCER</a>, ((<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">TIM_CCER_CC1NP</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a>) &lt;&lt; SHIFT_TAB_CCxP[iChannel])) &gt;&gt;</div>
<div class="line"><a id="l03130" name="l03130"></a><span class="lineno"> 3130</span>          SHIFT_TAB_CCxP[iChannel]);</div>
<div class="line"><a id="l03131" name="l03131"></a><span class="lineno"> 3131</span>}</div>
<div class="line"><a id="l03132" name="l03132"></a><span class="lineno"> 3132</span></div>
<div class="line"><a id="l03141" name="l03141"></a><span class="lineno"> 3141</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_IC_EnableXORCombination(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03142" name="l03142"></a><span class="lineno"> 3142</span>{</div>
<div class="line"><a id="l03143" name="l03143"></a><span class="lineno"> 3143</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">TIM_CR2_TI1S</a>);</div>
<div class="line"><a id="l03144" name="l03144"></a><span class="lineno"> 3144</span>}</div>
<div class="line"><a id="l03145" name="l03145"></a><span class="lineno"> 3145</span></div>
<div class="line"><a id="l03154" name="l03154"></a><span class="lineno"> 3154</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_IC_DisableXORCombination(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03155" name="l03155"></a><span class="lineno"> 3155</span>{</div>
<div class="line"><a id="l03156" name="l03156"></a><span class="lineno"> 3156</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">TIM_CR2_TI1S</a>);</div>
<div class="line"><a id="l03157" name="l03157"></a><span class="lineno"> 3157</span>}</div>
<div class="line"><a id="l03158" name="l03158"></a><span class="lineno"> 3158</span></div>
<div class="line"><a id="l03167" name="l03167"></a><span class="lineno"> 3167</span>__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03168" name="l03168"></a><span class="lineno"> 3168</span>{</div>
<div class="line"><a id="l03169" name="l03169"></a><span class="lineno"> 3169</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">TIM_CR2_TI1S</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">TIM_CR2_TI1S</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l03170" name="l03170"></a><span class="lineno"> 3170</span>}</div>
<div class="line"><a id="l03171" name="l03171"></a><span class="lineno"> 3171</span></div>
<div class="line"><a id="l03183" name="l03183"></a><span class="lineno"> 3183</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03184" name="l03184"></a><span class="lineno"> 3184</span>{</div>
<div class="line"><a id="l03185" name="l03185"></a><span class="lineno"> 3185</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a0dd9c06729a5eb6179c6d0d60faca7ed">CCR1</a>));</div>
<div class="line"><a id="l03186" name="l03186"></a><span class="lineno"> 3186</span>}</div>
<div class="line"><a id="l03187" name="l03187"></a><span class="lineno"> 3187</span></div>
<div class="line"><a id="l03199" name="l03199"></a><span class="lineno"> 3199</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03200" name="l03200"></a><span class="lineno"> 3200</span>{</div>
<div class="line"><a id="l03201" name="l03201"></a><span class="lineno"> 3201</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a4d1171e9a61538424b8ef1f2571986d0">CCR2</a>));</div>
<div class="line"><a id="l03202" name="l03202"></a><span class="lineno"> 3202</span>}</div>
<div class="line"><a id="l03203" name="l03203"></a><span class="lineno"> 3203</span></div>
<div class="line"><a id="l03215" name="l03215"></a><span class="lineno"> 3215</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03216" name="l03216"></a><span class="lineno"> 3216</span>{</div>
<div class="line"><a id="l03217" name="l03217"></a><span class="lineno"> 3217</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#ac83441bfb8d0287080dcbd945a272a74">CCR3</a>));</div>
<div class="line"><a id="l03218" name="l03218"></a><span class="lineno"> 3218</span>}</div>
<div class="line"><a id="l03219" name="l03219"></a><span class="lineno"> 3219</span></div>
<div class="line"><a id="l03231" name="l03231"></a><span class="lineno"> 3231</span>__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03232" name="l03232"></a><span class="lineno"> 3232</span>{</div>
<div class="line"><a id="l03233" name="l03233"></a><span class="lineno"> 3233</span>  <span class="keywordflow">return</span> (uint32_t)(READ_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a5ba381c3f312fdf5e0b4119641b3b0aa">CCR4</a>));</div>
<div class="line"><a id="l03234" name="l03234"></a><span class="lineno"> 3234</span>}</div>
<div class="line"><a id="l03235" name="l03235"></a><span class="lineno"> 3235</span></div>
<div class="line"><a id="l03239" name="l03239"></a><span class="lineno"> 3239</span></div>
<div class="line"><a id="l03252" name="l03252"></a><span class="lineno"> 3252</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableExternalClock(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03253" name="l03253"></a><span class="lineno"> 3253</span>{</div>
<div class="line"><a id="l03254" name="l03254"></a><span class="lineno"> 3254</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">TIM_SMCR_ECE</a>);</div>
<div class="line"><a id="l03255" name="l03255"></a><span class="lineno"> 3255</span>}</div>
<div class="line"><a id="l03256" name="l03256"></a><span class="lineno"> 3256</span></div>
<div class="line"><a id="l03265" name="l03265"></a><span class="lineno"> 3265</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableExternalClock(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03266" name="l03266"></a><span class="lineno"> 3266</span>{</div>
<div class="line"><a id="l03267" name="l03267"></a><span class="lineno"> 3267</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">TIM_SMCR_ECE</a>);</div>
<div class="line"><a id="l03268" name="l03268"></a><span class="lineno"> 3268</span>}</div>
<div class="line"><a id="l03269" name="l03269"></a><span class="lineno"> 3269</span></div>
<div class="line"><a id="l03278" name="l03278"></a><span class="lineno"> 3278</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03279" name="l03279"></a><span class="lineno"> 3279</span>{</div>
<div class="line"><a id="l03280" name="l03280"></a><span class="lineno"> 3280</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">TIM_SMCR_ECE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">TIM_SMCR_ECE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l03281" name="l03281"></a><span class="lineno"> 3281</span>}</div>
<div class="line"><a id="l03282" name="l03282"></a><span class="lineno"> 3282</span></div>
<div class="line"><a id="l03302" name="l03302"></a><span class="lineno"> 3302</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetClockSource(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t ClockSource)</div>
<div class="line"><a id="l03303" name="l03303"></a><span class="lineno"> 3303</span>{</div>
<div class="line"><a id="l03304" name="l03304"></a><span class="lineno"> 3304</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea">TIM_SMCR_SMS</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">TIM_SMCR_ECE</a>, ClockSource);</div>
<div class="line"><a id="l03305" name="l03305"></a><span class="lineno"> 3305</span>}</div>
<div class="line"><a id="l03306" name="l03306"></a><span class="lineno"> 3306</span></div>
<div class="line"><a id="l03319" name="l03319"></a><span class="lineno"> 3319</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetEncoderMode(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t EncoderMode)</div>
<div class="line"><a id="l03320" name="l03320"></a><span class="lineno"> 3320</span>{</div>
<div class="line"><a id="l03321" name="l03321"></a><span class="lineno"> 3321</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea">TIM_SMCR_SMS</a>, EncoderMode);</div>
<div class="line"><a id="l03322" name="l03322"></a><span class="lineno"> 3322</span>}</div>
<div class="line"><a id="l03323" name="l03323"></a><span class="lineno"> 3323</span></div>
<div class="line"><a id="l03327" name="l03327"></a><span class="lineno"> 3327</span></div>
<div class="line"><a id="l03348" name="l03348"></a><span class="lineno"> 3348</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetTriggerOutput(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t TimerSynchronization)</div>
<div class="line"><a id="l03349" name="l03349"></a><span class="lineno"> 3349</span>{</div>
<div class="line"><a id="l03350" name="l03350"></a><span class="lineno"> 3350</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaaa6987d980e5c4c71c7d0faa1eb97a45">TIM_CR2_MMS</a>, TimerSynchronization);</div>
<div class="line"><a id="l03351" name="l03351"></a><span class="lineno"> 3351</span>}</div>
<div class="line"><a id="l03352" name="l03352"></a><span class="lineno"> 3352</span></div>
<div class="line"><a id="l03378" name="l03378"></a><span class="lineno"> 3378</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetTriggerOutput2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t ADCSynchronization)</div>
<div class="line"><a id="l03379" name="l03379"></a><span class="lineno"> 3379</span>{</div>
<div class="line"><a id="l03380" name="l03380"></a><span class="lineno"> 3380</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">CR2</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae199132077792fb8efa01b87edd1c033">TIM_CR2_MMS2</a>, ADCSynchronization);</div>
<div class="line"><a id="l03381" name="l03381"></a><span class="lineno"> 3381</span>}</div>
<div class="line"><a id="l03382" name="l03382"></a><span class="lineno"> 3382</span></div>
<div class="line"><a id="l03397" name="l03397"></a><span class="lineno"> 3397</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetSlaveMode(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t SlaveMode)</div>
<div class="line"><a id="l03398" name="l03398"></a><span class="lineno"> 3398</span>{</div>
<div class="line"><a id="l03399" name="l03399"></a><span class="lineno"> 3399</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea">TIM_SMCR_SMS</a>, SlaveMode);</div>
<div class="line"><a id="l03400" name="l03400"></a><span class="lineno"> 3400</span>}</div>
<div class="line"><a id="l03401" name="l03401"></a><span class="lineno"> 3401</span></div>
<div class="line"><a id="l03431" name="l03431"></a><span class="lineno"> 3431</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetTriggerInput(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t TriggerInput)</div>
<div class="line"><a id="l03432" name="l03432"></a><span class="lineno"> 3432</span>{</div>
<div class="line"><a id="l03433" name="l03433"></a><span class="lineno"> 3433</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga8680e719bca2b672d850504220ae51fc">TIM_SMCR_TS</a>, TriggerInput);</div>
<div class="line"><a id="l03434" name="l03434"></a><span class="lineno"> 3434</span>}</div>
<div class="line"><a id="l03435" name="l03435"></a><span class="lineno"> 3435</span></div>
<div class="line"><a id="l03444" name="l03444"></a><span class="lineno"> 3444</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableMasterSlaveMode(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03445" name="l03445"></a><span class="lineno"> 3445</span>{</div>
<div class="line"><a id="l03446" name="l03446"></a><span class="lineno"> 3446</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">TIM_SMCR_MSM</a>);</div>
<div class="line"><a id="l03447" name="l03447"></a><span class="lineno"> 3447</span>}</div>
<div class="line"><a id="l03448" name="l03448"></a><span class="lineno"> 3448</span></div>
<div class="line"><a id="l03457" name="l03457"></a><span class="lineno"> 3457</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableMasterSlaveMode(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03458" name="l03458"></a><span class="lineno"> 3458</span>{</div>
<div class="line"><a id="l03459" name="l03459"></a><span class="lineno"> 3459</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">TIM_SMCR_MSM</a>);</div>
<div class="line"><a id="l03460" name="l03460"></a><span class="lineno"> 3460</span>}</div>
<div class="line"><a id="l03461" name="l03461"></a><span class="lineno"> 3461</span></div>
<div class="line"><a id="l03470" name="l03470"></a><span class="lineno"> 3470</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03471" name="l03471"></a><span class="lineno"> 3471</span>{</div>
<div class="line"><a id="l03472" name="l03472"></a><span class="lineno"> 3472</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">TIM_SMCR_MSM</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">TIM_SMCR_MSM</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l03473" name="l03473"></a><span class="lineno"> 3473</span>}</div>
<div class="line"><a id="l03474" name="l03474"></a><span class="lineno"> 3474</span></div>
<div class="line"><a id="l03510" name="l03510"></a><span class="lineno"> 3510</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ConfigETR(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,</div>
<div class="line"><a id="l03511" name="l03511"></a><span class="lineno"> 3511</span>                                      uint32_t ETRFilter)</div>
<div class="line"><a id="l03512" name="l03512"></a><span class="lineno"> 3512</span>{</div>
<div class="line"><a id="l03513" name="l03513"></a><span class="lineno"> 3513</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">SMCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga2a5f335c3d7a4f82d1e91dc1511e3322">TIM_SMCR_ETP</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ebb9e631876435e276211d88e797386">TIM_SMCR_ETPS</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae2ed8b32d9eb8eea251bd1dac4f34668">TIM_SMCR_ETF</a>, ETRPolarity | ETRPrescaler | ETRFilter);</div>
<div class="line"><a id="l03514" name="l03514"></a><span class="lineno"> 3514</span>}</div>
<div class="line"><a id="l03515" name="l03515"></a><span class="lineno"> 3515</span></div>
<div class="line"><a id="l03579" name="l03579"></a><span class="lineno"> 3579</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetETRSource(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t ETRSource)</div>
<div class="line"><a id="l03580" name="l03580"></a><span class="lineno"> 3580</span>{</div>
<div class="line"><a id="l03581" name="l03581"></a><span class="lineno"> 3581</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a7a81e7aac9bef80b126097f8e9f36d07">AF1</a>, TIMx_AF1_ETRSEL, ETRSource);</div>
<div class="line"><a id="l03582" name="l03582"></a><span class="lineno"> 3582</span>}</div>
<div class="line"><a id="l03583" name="l03583"></a><span class="lineno"> 3583</span></div>
<div class="line"><a id="l03587" name="l03587"></a><span class="lineno"> 3587</span></div>
<div class="line"><a id="l03599" name="l03599"></a><span class="lineno"> 3599</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableBRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03600" name="l03600"></a><span class="lineno"> 3600</span>{</div>
<div class="line"><a id="l03601" name="l03601"></a><span class="lineno"> 3601</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8">TIM_BDTR_BKE</a>);</div>
<div class="line"><a id="l03602" name="l03602"></a><span class="lineno"> 3602</span>}</div>
<div class="line"><a id="l03603" name="l03603"></a><span class="lineno"> 3603</span></div>
<div class="line"><a id="l03612" name="l03612"></a><span class="lineno"> 3612</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableBRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03613" name="l03613"></a><span class="lineno"> 3613</span>{</div>
<div class="line"><a id="l03614" name="l03614"></a><span class="lineno"> 3614</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8">TIM_BDTR_BKE</a>);</div>
<div class="line"><a id="l03615" name="l03615"></a><span class="lineno"> 3615</span>}</div>
<div class="line"><a id="l03616" name="l03616"></a><span class="lineno"> 3616</span> </div>
<div class="line"><a id="l03617" name="l03617"></a><span class="lineno"> 3617</span><span class="preprocessor">#if defined(TIM_BDTR_BKBID)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03660" name="l03660"></a><span class="lineno"> 3660</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ConfigBRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,</div>
<div class="line"><a id="l03661" name="l03661"></a><span class="lineno"> 3661</span>                                      uint32_t BreakAFMode)</div>
<div class="line"><a id="l03662" name="l03662"></a><span class="lineno"> 3662</span>{</div>
<div class="line"><a id="l03663" name="l03663"></a><span class="lineno"> 3663</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e">TIM_BDTR_BKP</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae2be17c432a12ce3ec4a79aa380a01b6">TIM_BDTR_BKF</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga58c65231de95b67cb2d115064ab57f60">TIM_BDTR_BKBID</a>, BreakPolarity | BreakFilter | BreakAFMode);</div>
<div class="line"><a id="l03664" name="l03664"></a><span class="lineno"> 3664</span>}</div>
<div class="line"><a id="l03665" name="l03665"></a><span class="lineno"> 3665</span> </div>
<div class="line"><a id="l03666" name="l03666"></a><span class="lineno"> 3666</span><span class="preprocessor">#else</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03696" name="l03696"></a><span class="lineno"> 3696</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ConfigBRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t BreakPolarity,</div>
<div class="line"><a id="l03697" name="l03697"></a><span class="lineno"> 3697</span>                                      uint32_t BreakFilter)</div>
<div class="line"><a id="l03698" name="l03698"></a><span class="lineno"> 3698</span>{</div>
<div class="line"><a id="l03699" name="l03699"></a><span class="lineno"> 3699</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e">TIM_BDTR_BKP</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae2be17c432a12ce3ec4a79aa380a01b6">TIM_BDTR_BKF</a>, BreakPolarity | BreakFilter);</div>
<div class="line"><a id="l03700" name="l03700"></a><span class="lineno"> 3700</span>}</div>
<div class="line"><a id="l03701" name="l03701"></a><span class="lineno"> 3701</span> </div>
<div class="line"><a id="l03702" name="l03702"></a><span class="lineno"> 3702</span><span class="preprocessor">#endif </span><span class="comment">/* TIM_BDTR_BKBID */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03703" name="l03703"></a><span class="lineno"> 3703</span><span class="preprocessor">#if defined(TIM_BDTR_BKBID)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03714" name="l03714"></a><span class="lineno"> 3714</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisarmBRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03715" name="l03715"></a><span class="lineno"> 3715</span>{</div>
<div class="line"><a id="l03716" name="l03716"></a><span class="lineno"> 3716</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga2ed336e59081fe830617f97dcb71678b">TIM_BDTR_BKDSRM</a>);</div>
<div class="line"><a id="l03717" name="l03717"></a><span class="lineno"> 3717</span>}</div>
<div class="line"><a id="l03718" name="l03718"></a><span class="lineno"> 3718</span> </div>
<div class="line"><a id="l03719" name="l03719"></a><span class="lineno"> 3719</span><span class="preprocessor">#endif </span><span class="comment">/*TIM_BDTR_BKBID */</span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l03728" name="l03728"></a><span class="lineno"> 3728</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableBRK2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03729" name="l03729"></a><span class="lineno"> 3729</span>{</div>
<div class="line"><a id="l03730" name="l03730"></a><span class="lineno"> 3730</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga50aff10d1577a94de8c4aa46cd2cbdb5">TIM_BDTR_BK2E</a>);</div>
<div class="line"><a id="l03731" name="l03731"></a><span class="lineno"> 3731</span>}</div>
<div class="line"><a id="l03732" name="l03732"></a><span class="lineno"> 3732</span></div>
<div class="line"><a id="l03741" name="l03741"></a><span class="lineno"> 3741</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableBRK2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03742" name="l03742"></a><span class="lineno"> 3742</span>{</div>
<div class="line"><a id="l03743" name="l03743"></a><span class="lineno"> 3743</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga50aff10d1577a94de8c4aa46cd2cbdb5">TIM_BDTR_BK2E</a>);</div>
<div class="line"><a id="l03744" name="l03744"></a><span class="lineno"> 3744</span>}</div>
<div class="line"><a id="l03745" name="l03745"></a><span class="lineno"> 3745</span> </div>
<div class="line"><a id="l03746" name="l03746"></a><span class="lineno"> 3746</span><span class="preprocessor">#if defined(TIM_BDTR_BKBID)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03789" name="l03789"></a><span class="lineno"> 3789</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ConfigBRK2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,</div>
<div class="line"><a id="l03790" name="l03790"></a><span class="lineno"> 3790</span>                                       uint32_t Break2AFMode)</div>
<div class="line"><a id="l03791" name="l03791"></a><span class="lineno"> 3791</span>{</div>
<div class="line"><a id="l03792" name="l03792"></a><span class="lineno"> 3792</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga94911ade52aef76f5ad41613f9fc9590">TIM_BDTR_BK2P</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacb338853d60dffd23d45fc67b6649705">TIM_BDTR_BK2F</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab3c8126b8cc13f3338b59f1e91202d43">TIM_BDTR_BK2BID</a>, Break2Polarity | Break2Filter | Break2AFMode);</div>
<div class="line"><a id="l03793" name="l03793"></a><span class="lineno"> 3793</span>}</div>
<div class="line"><a id="l03794" name="l03794"></a><span class="lineno"> 3794</span> </div>
<div class="line"><a id="l03795" name="l03795"></a><span class="lineno"> 3795</span><span class="preprocessor">#else</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03825" name="l03825"></a><span class="lineno"> 3825</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ConfigBRK2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)</div>
<div class="line"><a id="l03826" name="l03826"></a><span class="lineno"> 3826</span>{</div>
<div class="line"><a id="l03827" name="l03827"></a><span class="lineno"> 3827</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga94911ade52aef76f5ad41613f9fc9590">TIM_BDTR_BK2P</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacb338853d60dffd23d45fc67b6649705">TIM_BDTR_BK2F</a>, Break2Polarity | Break2Filter);</div>
<div class="line"><a id="l03828" name="l03828"></a><span class="lineno"> 3828</span>}</div>
<div class="line"><a id="l03829" name="l03829"></a><span class="lineno"> 3829</span> </div>
<div class="line"><a id="l03830" name="l03830"></a><span class="lineno"> 3830</span><span class="preprocessor">#endif </span><span class="comment">/*TIM_BDTR_BKBID */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03831" name="l03831"></a><span class="lineno"> 3831</span><span class="preprocessor">#if defined(TIM_BDTR_BKBID)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03842" name="l03842"></a><span class="lineno"> 3842</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisarmBRK2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03843" name="l03843"></a><span class="lineno"> 3843</span>{</div>
<div class="line"><a id="l03844" name="l03844"></a><span class="lineno"> 3844</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga759883f669298c750d8dbf3d2fd2fab2">TIM_BDTR_BK2DSRM</a>);</div>
<div class="line"><a id="l03845" name="l03845"></a><span class="lineno"> 3845</span>}</div>
<div class="line"><a id="l03846" name="l03846"></a><span class="lineno"> 3846</span> </div>
<div class="line"><a id="l03847" name="l03847"></a><span class="lineno"> 3847</span><span class="preprocessor">#endif </span><span class="comment">/*TIM_BDTR_BKBID */</span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l03863" name="l03863"></a><span class="lineno"> 3863</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetOffStates(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)</div>
<div class="line"><a id="l03864" name="l03864"></a><span class="lineno"> 3864</span>{</div>
<div class="line"><a id="l03865" name="l03865"></a><span class="lineno"> 3865</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab1cf04e70ccf3d4aba5afcf2496a411a">TIM_BDTR_OSSI</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf9435f36d53c6be1107e57ab6a82c16e">TIM_BDTR_OSSR</a>, OffStateIdle | OffStateRun);</div>
<div class="line"><a id="l03866" name="l03866"></a><span class="lineno"> 3866</span>}</div>
<div class="line"><a id="l03867" name="l03867"></a><span class="lineno"> 3867</span></div>
<div class="line"><a id="l03876" name="l03876"></a><span class="lineno"> 3876</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableAutomaticOutput(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03877" name="l03877"></a><span class="lineno"> 3877</span>{</div>
<div class="line"><a id="l03878" name="l03878"></a><span class="lineno"> 3878</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">TIM_BDTR_AOE</a>);</div>
<div class="line"><a id="l03879" name="l03879"></a><span class="lineno"> 3879</span>}</div>
<div class="line"><a id="l03880" name="l03880"></a><span class="lineno"> 3880</span></div>
<div class="line"><a id="l03889" name="l03889"></a><span class="lineno"> 3889</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableAutomaticOutput(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03890" name="l03890"></a><span class="lineno"> 3890</span>{</div>
<div class="line"><a id="l03891" name="l03891"></a><span class="lineno"> 3891</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">TIM_BDTR_AOE</a>);</div>
<div class="line"><a id="l03892" name="l03892"></a><span class="lineno"> 3892</span>}</div>
<div class="line"><a id="l03893" name="l03893"></a><span class="lineno"> 3893</span></div>
<div class="line"><a id="l03902" name="l03902"></a><span class="lineno"> 3902</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03903" name="l03903"></a><span class="lineno"> 3903</span>{</div>
<div class="line"><a id="l03904" name="l03904"></a><span class="lineno"> 3904</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">TIM_BDTR_AOE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">TIM_BDTR_AOE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l03905" name="l03905"></a><span class="lineno"> 3905</span>}</div>
<div class="line"><a id="l03906" name="l03906"></a><span class="lineno"> 3906</span></div>
<div class="line"><a id="l03917" name="l03917"></a><span class="lineno"> 3917</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableAllOutputs(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03918" name="l03918"></a><span class="lineno"> 3918</span>{</div>
<div class="line"><a id="l03919" name="l03919"></a><span class="lineno"> 3919</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">TIM_BDTR_MOE</a>);</div>
<div class="line"><a id="l03920" name="l03920"></a><span class="lineno"> 3920</span>}</div>
<div class="line"><a id="l03921" name="l03921"></a><span class="lineno"> 3921</span></div>
<div class="line"><a id="l03932" name="l03932"></a><span class="lineno"> 3932</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableAllOutputs(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03933" name="l03933"></a><span class="lineno"> 3933</span>{</div>
<div class="line"><a id="l03934" name="l03934"></a><span class="lineno"> 3934</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">TIM_BDTR_MOE</a>);</div>
<div class="line"><a id="l03935" name="l03935"></a><span class="lineno"> 3935</span>}</div>
<div class="line"><a id="l03936" name="l03936"></a><span class="lineno"> 3936</span></div>
<div class="line"><a id="l03945" name="l03945"></a><span class="lineno"> 3945</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l03946" name="l03946"></a><span class="lineno"> 3946</span>{</div>
<div class="line"><a id="l03947" name="l03947"></a><span class="lineno"> 3947</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">BDTR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">TIM_BDTR_MOE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">TIM_BDTR_MOE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l03948" name="l03948"></a><span class="lineno"> 3948</span>}</div>
<div class="line"><a id="l03949" name="l03949"></a><span class="lineno"> 3949</span> </div>
<div class="line"><a id="l03950" name="l03950"></a><span class="lineno"> 3950</span><span class="preprocessor">#if defined(TIM_BREAK_INPUT_SUPPORT)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03974" name="l03974"></a><span class="lineno"> 3974</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableBreakInputSource(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t BreakInput, uint32_t Source)</div>
<div class="line"><a id="l03975" name="l03975"></a><span class="lineno"> 3975</span>{</div>
<div class="line"><a id="l03976" name="l03976"></a><span class="lineno"> 3976</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a7a81e7aac9bef80b126097f8e9f36d07">AF1</a>) + BreakInput));</div>
<div class="line"><a id="l03977" name="l03977"></a><span class="lineno"> 3977</span>  SET_BIT(*pReg, Source);</div>
<div class="line"><a id="l03978" name="l03978"></a><span class="lineno"> 3978</span>}</div>
<div class="line"><a id="l03979" name="l03979"></a><span class="lineno"> 3979</span></div>
<div class="line"><a id="l04003" name="l04003"></a><span class="lineno"> 4003</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableBreakInputSource(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t BreakInput, uint32_t Source)</div>
<div class="line"><a id="l04004" name="l04004"></a><span class="lineno"> 4004</span>{</div>
<div class="line"><a id="l04005" name="l04005"></a><span class="lineno"> 4005</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a7a81e7aac9bef80b126097f8e9f36d07">AF1</a>) + BreakInput));</div>
<div class="line"><a id="l04006" name="l04006"></a><span class="lineno"> 4006</span>  CLEAR_BIT(*pReg, Source);</div>
<div class="line"><a id="l04007" name="l04007"></a><span class="lineno"> 4007</span>}</div>
<div class="line"><a id="l04008" name="l04008"></a><span class="lineno"> 4008</span></div>
<div class="line"><a id="l04032" name="l04032"></a><span class="lineno"> 4032</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetBreakInputSourcePolarity(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t BreakInput, uint32_t Source,</div>
<div class="line"><a id="l04033" name="l04033"></a><span class="lineno"> 4033</span>                                                        uint32_t Polarity)</div>
<div class="line"><a id="l04034" name="l04034"></a><span class="lineno"> 4034</span>{</div>
<div class="line"><a id="l04035" name="l04035"></a><span class="lineno"> 4035</span>  <a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *pReg = (<a class="code hl_define" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t *)((uint32_t)((uint32_t)(&amp;TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a7a81e7aac9bef80b126097f8e9f36d07">AF1</a>) + BreakInput));</div>
<div class="line"><a id="l04036" name="l04036"></a><span class="lineno"> 4036</span>  MODIFY_REG(*pReg, (TIMx_AF1_BKINP &lt;&lt; TIM_POSITION_BRK_SOURCE), (Polarity &lt;&lt; TIM_POSITION_BRK_SOURCE));</div>
<div class="line"><a id="l04037" name="l04037"></a><span class="lineno"> 4037</span>}</div>
<div class="line"><a id="l04038" name="l04038"></a><span class="lineno"> 4038</span><span class="preprocessor">#endif </span><span class="comment">/* TIM_BREAK_INPUT_SUPPORT */</span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l04042" name="l04042"></a><span class="lineno"> 4042</span></div>
<div class="line"><a id="l04100" name="l04100"></a><span class="lineno"> 4100</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ConfigDMABurst(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)</div>
<div class="line"><a id="l04101" name="l04101"></a><span class="lineno"> 4101</span>{</div>
<div class="line"><a id="l04102" name="l04102"></a><span class="lineno"> 4102</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a7efe9ea8067044cac449ada756ebc2d1">DCR</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9e197a78484567d4c6093c28265f3eb">TIM_DCR_DBL</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gabf9051ecac123cd89f9d2a835e4cde2e">TIM_DCR_DBA</a>), (DMABurstBaseAddress | DMABurstLength));</div>
<div class="line"><a id="l04103" name="l04103"></a><span class="lineno"> 4103</span>}</div>
<div class="line"><a id="l04104" name="l04104"></a><span class="lineno"> 4104</span></div>
<div class="line"><a id="l04108" name="l04108"></a><span class="lineno"> 4108</span></div>
<div class="line"><a id="l04185" name="l04185"></a><span class="lineno"> 4185</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_SetRemap(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Remap)</div>
<div class="line"><a id="l04186" name="l04186"></a><span class="lineno"> 4186</span>{</div>
<div class="line"><a id="l04187" name="l04187"></a><span class="lineno"> 4187</span>  MODIFY_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a48ce9972eb643ae4f34bd75a0b931ad4">TISEL</a>, (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5168e7f269c569c733b656bb86b5c3a5">TIM_TISEL_TI1SEL</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaff4d8ae0f229b42960fe34be62a3b499">TIM_TISEL_TI2SEL</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7c19a6840ec57afc1b9ae48703f60fc1">TIM_TISEL_TI3SEL</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7eff9d6247daaa7bdbd6f009ab80d595">TIM_TISEL_TI4SEL</a>), Remap);</div>
<div class="line"><a id="l04188" name="l04188"></a><span class="lineno"> 4188</span>}</div>
<div class="line"><a id="l04189" name="l04189"></a><span class="lineno"> 4189</span></div>
<div class="line"><a id="l04193" name="l04193"></a><span class="lineno"> 4193</span></div>
<div class="line"><a id="l04203" name="l04203"></a><span class="lineno"> 4203</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_UPDATE(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04204" name="l04204"></a><span class="lineno"> 4204</span>{</div>
<div class="line"><a id="l04205" name="l04205"></a><span class="lineno"> 4205</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6">TIM_SR_UIF</a>));</div>
<div class="line"><a id="l04206" name="l04206"></a><span class="lineno"> 4206</span>}</div>
<div class="line"><a id="l04207" name="l04207"></a><span class="lineno"> 4207</span></div>
<div class="line"><a id="l04214" name="l04214"></a><span class="lineno"> 4214</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04215" name="l04215"></a><span class="lineno"> 4215</span>{</div>
<div class="line"><a id="l04216" name="l04216"></a><span class="lineno"> 4216</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6">TIM_SR_UIF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6">TIM_SR_UIF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04217" name="l04217"></a><span class="lineno"> 4217</span>}</div>
<div class="line"><a id="l04218" name="l04218"></a><span class="lineno"> 4218</span></div>
<div class="line"><a id="l04225" name="l04225"></a><span class="lineno"> 4225</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC1(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04226" name="l04226"></a><span class="lineno"> 4226</span>{</div>
<div class="line"><a id="l04227" name="l04227"></a><span class="lineno"> 4227</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9">TIM_SR_CC1IF</a>));</div>
<div class="line"><a id="l04228" name="l04228"></a><span class="lineno"> 4228</span>}</div>
<div class="line"><a id="l04229" name="l04229"></a><span class="lineno"> 4229</span></div>
<div class="line"><a id="l04236" name="l04236"></a><span class="lineno"> 4236</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04237" name="l04237"></a><span class="lineno"> 4237</span>{</div>
<div class="line"><a id="l04238" name="l04238"></a><span class="lineno"> 4238</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9">TIM_SR_CC1IF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9">TIM_SR_CC1IF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04239" name="l04239"></a><span class="lineno"> 4239</span>}</div>
<div class="line"><a id="l04240" name="l04240"></a><span class="lineno"> 4240</span></div>
<div class="line"><a id="l04247" name="l04247"></a><span class="lineno"> 4247</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04248" name="l04248"></a><span class="lineno"> 4248</span>{</div>
<div class="line"><a id="l04249" name="l04249"></a><span class="lineno"> 4249</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8">TIM_SR_CC2IF</a>));</div>
<div class="line"><a id="l04250" name="l04250"></a><span class="lineno"> 4250</span>}</div>
<div class="line"><a id="l04251" name="l04251"></a><span class="lineno"> 4251</span></div>
<div class="line"><a id="l04258" name="l04258"></a><span class="lineno"> 4258</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04259" name="l04259"></a><span class="lineno"> 4259</span>{</div>
<div class="line"><a id="l04260" name="l04260"></a><span class="lineno"> 4260</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8">TIM_SR_CC2IF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8">TIM_SR_CC2IF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04261" name="l04261"></a><span class="lineno"> 4261</span>}</div>
<div class="line"><a id="l04262" name="l04262"></a><span class="lineno"> 4262</span></div>
<div class="line"><a id="l04269" name="l04269"></a><span class="lineno"> 4269</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC3(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04270" name="l04270"></a><span class="lineno"> 4270</span>{</div>
<div class="line"><a id="l04271" name="l04271"></a><span class="lineno"> 4271</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2">TIM_SR_CC3IF</a>));</div>
<div class="line"><a id="l04272" name="l04272"></a><span class="lineno"> 4272</span>}</div>
<div class="line"><a id="l04273" name="l04273"></a><span class="lineno"> 4273</span></div>
<div class="line"><a id="l04280" name="l04280"></a><span class="lineno"> 4280</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04281" name="l04281"></a><span class="lineno"> 4281</span>{</div>
<div class="line"><a id="l04282" name="l04282"></a><span class="lineno"> 4282</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2">TIM_SR_CC3IF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2">TIM_SR_CC3IF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04283" name="l04283"></a><span class="lineno"> 4283</span>}</div>
<div class="line"><a id="l04284" name="l04284"></a><span class="lineno"> 4284</span></div>
<div class="line"><a id="l04291" name="l04291"></a><span class="lineno"> 4291</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC4(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04292" name="l04292"></a><span class="lineno"> 4292</span>{</div>
<div class="line"><a id="l04293" name="l04293"></a><span class="lineno"> 4293</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac">TIM_SR_CC4IF</a>));</div>
<div class="line"><a id="l04294" name="l04294"></a><span class="lineno"> 4294</span>}</div>
<div class="line"><a id="l04295" name="l04295"></a><span class="lineno"> 4295</span></div>
<div class="line"><a id="l04302" name="l04302"></a><span class="lineno"> 4302</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04303" name="l04303"></a><span class="lineno"> 4303</span>{</div>
<div class="line"><a id="l04304" name="l04304"></a><span class="lineno"> 4304</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac">TIM_SR_CC4IF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac">TIM_SR_CC4IF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04305" name="l04305"></a><span class="lineno"> 4305</span>}</div>
<div class="line"><a id="l04306" name="l04306"></a><span class="lineno"> 4306</span></div>
<div class="line"><a id="l04313" name="l04313"></a><span class="lineno"> 4313</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC5(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04314" name="l04314"></a><span class="lineno"> 4314</span>{</div>
<div class="line"><a id="l04315" name="l04315"></a><span class="lineno"> 4315</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga2167773377ba03c863cc49342c67789f">TIM_SR_CC5IF</a>));</div>
<div class="line"><a id="l04316" name="l04316"></a><span class="lineno"> 4316</span>}</div>
<div class="line"><a id="l04317" name="l04317"></a><span class="lineno"> 4317</span></div>
<div class="line"><a id="l04324" name="l04324"></a><span class="lineno"> 4324</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04325" name="l04325"></a><span class="lineno"> 4325</span>{</div>
<div class="line"><a id="l04326" name="l04326"></a><span class="lineno"> 4326</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga2167773377ba03c863cc49342c67789f">TIM_SR_CC5IF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga2167773377ba03c863cc49342c67789f">TIM_SR_CC5IF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04327" name="l04327"></a><span class="lineno"> 4327</span>}</div>
<div class="line"><a id="l04328" name="l04328"></a><span class="lineno"> 4328</span></div>
<div class="line"><a id="l04335" name="l04335"></a><span class="lineno"> 4335</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC6(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04336" name="l04336"></a><span class="lineno"> 4336</span>{</div>
<div class="line"><a id="l04337" name="l04337"></a><span class="lineno"> 4337</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad16e2f81b0c4fe28e323f3302c2240db">TIM_SR_CC6IF</a>));</div>
<div class="line"><a id="l04338" name="l04338"></a><span class="lineno"> 4338</span>}</div>
<div class="line"><a id="l04339" name="l04339"></a><span class="lineno"> 4339</span></div>
<div class="line"><a id="l04346" name="l04346"></a><span class="lineno"> 4346</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04347" name="l04347"></a><span class="lineno"> 4347</span>{</div>
<div class="line"><a id="l04348" name="l04348"></a><span class="lineno"> 4348</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad16e2f81b0c4fe28e323f3302c2240db">TIM_SR_CC6IF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad16e2f81b0c4fe28e323f3302c2240db">TIM_SR_CC6IF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04349" name="l04349"></a><span class="lineno"> 4349</span>}</div>
<div class="line"><a id="l04350" name="l04350"></a><span class="lineno"> 4350</span></div>
<div class="line"><a id="l04357" name="l04357"></a><span class="lineno"> 4357</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_COM(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04358" name="l04358"></a><span class="lineno"> 4358</span>{</div>
<div class="line"><a id="l04359" name="l04359"></a><span class="lineno"> 4359</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a">TIM_SR_COMIF</a>));</div>
<div class="line"><a id="l04360" name="l04360"></a><span class="lineno"> 4360</span>}</div>
<div class="line"><a id="l04361" name="l04361"></a><span class="lineno"> 4361</span></div>
<div class="line"><a id="l04368" name="l04368"></a><span class="lineno"> 4368</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04369" name="l04369"></a><span class="lineno"> 4369</span>{</div>
<div class="line"><a id="l04370" name="l04370"></a><span class="lineno"> 4370</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a">TIM_SR_COMIF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a">TIM_SR_COMIF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04371" name="l04371"></a><span class="lineno"> 4371</span>}</div>
<div class="line"><a id="l04372" name="l04372"></a><span class="lineno"> 4372</span></div>
<div class="line"><a id="l04379" name="l04379"></a><span class="lineno"> 4379</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_TRIG(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04380" name="l04380"></a><span class="lineno"> 4380</span>{</div>
<div class="line"><a id="l04381" name="l04381"></a><span class="lineno"> 4381</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e">TIM_SR_TIF</a>));</div>
<div class="line"><a id="l04382" name="l04382"></a><span class="lineno"> 4382</span>}</div>
<div class="line"><a id="l04383" name="l04383"></a><span class="lineno"> 4383</span></div>
<div class="line"><a id="l04390" name="l04390"></a><span class="lineno"> 4390</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04391" name="l04391"></a><span class="lineno"> 4391</span>{</div>
<div class="line"><a id="l04392" name="l04392"></a><span class="lineno"> 4392</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e">TIM_SR_TIF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e">TIM_SR_TIF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04393" name="l04393"></a><span class="lineno"> 4393</span>}</div>
<div class="line"><a id="l04394" name="l04394"></a><span class="lineno"> 4394</span></div>
<div class="line"><a id="l04401" name="l04401"></a><span class="lineno"> 4401</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_BRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04402" name="l04402"></a><span class="lineno"> 4402</span>{</div>
<div class="line"><a id="l04403" name="l04403"></a><span class="lineno"> 4403</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097">TIM_SR_BIF</a>));</div>
<div class="line"><a id="l04404" name="l04404"></a><span class="lineno"> 4404</span>}</div>
<div class="line"><a id="l04405" name="l04405"></a><span class="lineno"> 4405</span></div>
<div class="line"><a id="l04412" name="l04412"></a><span class="lineno"> 4412</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04413" name="l04413"></a><span class="lineno"> 4413</span>{</div>
<div class="line"><a id="l04414" name="l04414"></a><span class="lineno"> 4414</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097">TIM_SR_BIF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097">TIM_SR_BIF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04415" name="l04415"></a><span class="lineno"> 4415</span>}</div>
<div class="line"><a id="l04416" name="l04416"></a><span class="lineno"> 4416</span></div>
<div class="line"><a id="l04423" name="l04423"></a><span class="lineno"> 4423</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_BRK2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04424" name="l04424"></a><span class="lineno"> 4424</span>{</div>
<div class="line"><a id="l04425" name="l04425"></a><span class="lineno"> 4425</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaef0c136d9338baf71a64ff650b385645">TIM_SR_B2IF</a>));</div>
<div class="line"><a id="l04426" name="l04426"></a><span class="lineno"> 4426</span>}</div>
<div class="line"><a id="l04427" name="l04427"></a><span class="lineno"> 4427</span></div>
<div class="line"><a id="l04434" name="l04434"></a><span class="lineno"> 4434</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04435" name="l04435"></a><span class="lineno"> 4435</span>{</div>
<div class="line"><a id="l04436" name="l04436"></a><span class="lineno"> 4436</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaef0c136d9338baf71a64ff650b385645">TIM_SR_B2IF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaef0c136d9338baf71a64ff650b385645">TIM_SR_B2IF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04437" name="l04437"></a><span class="lineno"> 4437</span>}</div>
<div class="line"><a id="l04438" name="l04438"></a><span class="lineno"> 4438</span></div>
<div class="line"><a id="l04445" name="l04445"></a><span class="lineno"> 4445</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC1OVR(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04446" name="l04446"></a><span class="lineno"> 4446</span>{</div>
<div class="line"><a id="l04447" name="l04447"></a><span class="lineno"> 4447</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c">TIM_SR_CC1OF</a>));</div>
<div class="line"><a id="l04448" name="l04448"></a><span class="lineno"> 4448</span>}</div>
<div class="line"><a id="l04449" name="l04449"></a><span class="lineno"> 4449</span></div>
<div class="line"><a id="l04457" name="l04457"></a><span class="lineno"> 4457</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04458" name="l04458"></a><span class="lineno"> 4458</span>{</div>
<div class="line"><a id="l04459" name="l04459"></a><span class="lineno"> 4459</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c">TIM_SR_CC1OF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c">TIM_SR_CC1OF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04460" name="l04460"></a><span class="lineno"> 4460</span>}</div>
<div class="line"><a id="l04461" name="l04461"></a><span class="lineno"> 4461</span></div>
<div class="line"><a id="l04468" name="l04468"></a><span class="lineno"> 4468</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC2OVR(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04469" name="l04469"></a><span class="lineno"> 4469</span>{</div>
<div class="line"><a id="l04470" name="l04470"></a><span class="lineno"> 4470</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050">TIM_SR_CC2OF</a>));</div>
<div class="line"><a id="l04471" name="l04471"></a><span class="lineno"> 4471</span>}</div>
<div class="line"><a id="l04472" name="l04472"></a><span class="lineno"> 4472</span></div>
<div class="line"><a id="l04480" name="l04480"></a><span class="lineno"> 4480</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04481" name="l04481"></a><span class="lineno"> 4481</span>{</div>
<div class="line"><a id="l04482" name="l04482"></a><span class="lineno"> 4482</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050">TIM_SR_CC2OF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050">TIM_SR_CC2OF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04483" name="l04483"></a><span class="lineno"> 4483</span>}</div>
<div class="line"><a id="l04484" name="l04484"></a><span class="lineno"> 4484</span></div>
<div class="line"><a id="l04491" name="l04491"></a><span class="lineno"> 4491</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC3OVR(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04492" name="l04492"></a><span class="lineno"> 4492</span>{</div>
<div class="line"><a id="l04493" name="l04493"></a><span class="lineno"> 4493</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358">TIM_SR_CC3OF</a>));</div>
<div class="line"><a id="l04494" name="l04494"></a><span class="lineno"> 4494</span>}</div>
<div class="line"><a id="l04495" name="l04495"></a><span class="lineno"> 4495</span></div>
<div class="line"><a id="l04503" name="l04503"></a><span class="lineno"> 4503</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04504" name="l04504"></a><span class="lineno"> 4504</span>{</div>
<div class="line"><a id="l04505" name="l04505"></a><span class="lineno"> 4505</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358">TIM_SR_CC3OF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358">TIM_SR_CC3OF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04506" name="l04506"></a><span class="lineno"> 4506</span>}</div>
<div class="line"><a id="l04507" name="l04507"></a><span class="lineno"> 4507</span></div>
<div class="line"><a id="l04514" name="l04514"></a><span class="lineno"> 4514</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_CC4OVR(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04515" name="l04515"></a><span class="lineno"> 4515</span>{</div>
<div class="line"><a id="l04516" name="l04516"></a><span class="lineno"> 4516</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740">TIM_SR_CC4OF</a>));</div>
<div class="line"><a id="l04517" name="l04517"></a><span class="lineno"> 4517</span>}</div>
<div class="line"><a id="l04518" name="l04518"></a><span class="lineno"> 4518</span></div>
<div class="line"><a id="l04526" name="l04526"></a><span class="lineno"> 4526</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04527" name="l04527"></a><span class="lineno"> 4527</span>{</div>
<div class="line"><a id="l04528" name="l04528"></a><span class="lineno"> 4528</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740">TIM_SR_CC4OF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740">TIM_SR_CC4OF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04529" name="l04529"></a><span class="lineno"> 4529</span>}</div>
<div class="line"><a id="l04530" name="l04530"></a><span class="lineno"> 4530</span></div>
<div class="line"><a id="l04537" name="l04537"></a><span class="lineno"> 4537</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_ClearFlag_SYSBRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04538" name="l04538"></a><span class="lineno"> 4538</span>{</div>
<div class="line"><a id="l04539" name="l04539"></a><span class="lineno"> 4539</span>  WRITE_REG(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, ~(<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae6c84655ac31844ff644f796ef638e06">TIM_SR_SBIF</a>));</div>
<div class="line"><a id="l04540" name="l04540"></a><span class="lineno"> 4540</span>}</div>
<div class="line"><a id="l04541" name="l04541"></a><span class="lineno"> 4541</span></div>
<div class="line"><a id="l04548" name="l04548"></a><span class="lineno"> 4548</span>__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04549" name="l04549"></a><span class="lineno"> 4549</span>{</div>
<div class="line"><a id="l04550" name="l04550"></a><span class="lineno"> 4550</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">SR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae6c84655ac31844ff644f796ef638e06">TIM_SR_SBIF</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae6c84655ac31844ff644f796ef638e06">TIM_SR_SBIF</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04551" name="l04551"></a><span class="lineno"> 4551</span>}</div>
<div class="line"><a id="l04552" name="l04552"></a><span class="lineno"> 4552</span></div>
<div class="line"><a id="l04556" name="l04556"></a><span class="lineno"> 4556</span></div>
<div class="line"><a id="l04566" name="l04566"></a><span class="lineno"> 4566</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_UPDATE(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04567" name="l04567"></a><span class="lineno"> 4567</span>{</div>
<div class="line"><a id="l04568" name="l04568"></a><span class="lineno"> 4568</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">TIM_DIER_UIE</a>);</div>
<div class="line"><a id="l04569" name="l04569"></a><span class="lineno"> 4569</span>}</div>
<div class="line"><a id="l04570" name="l04570"></a><span class="lineno"> 4570</span></div>
<div class="line"><a id="l04577" name="l04577"></a><span class="lineno"> 4577</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_UPDATE(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04578" name="l04578"></a><span class="lineno"> 4578</span>{</div>
<div class="line"><a id="l04579" name="l04579"></a><span class="lineno"> 4579</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">TIM_DIER_UIE</a>);</div>
<div class="line"><a id="l04580" name="l04580"></a><span class="lineno"> 4580</span>}</div>
<div class="line"><a id="l04581" name="l04581"></a><span class="lineno"> 4581</span></div>
<div class="line"><a id="l04588" name="l04588"></a><span class="lineno"> 4588</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04589" name="l04589"></a><span class="lineno"> 4589</span>{</div>
<div class="line"><a id="l04590" name="l04590"></a><span class="lineno"> 4590</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">TIM_DIER_UIE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">TIM_DIER_UIE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04591" name="l04591"></a><span class="lineno"> 4591</span>}</div>
<div class="line"><a id="l04592" name="l04592"></a><span class="lineno"> 4592</span></div>
<div class="line"><a id="l04599" name="l04599"></a><span class="lineno"> 4599</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_CC1(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04600" name="l04600"></a><span class="lineno"> 4600</span>{</div>
<div class="line"><a id="l04601" name="l04601"></a><span class="lineno"> 4601</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">TIM_DIER_CC1IE</a>);</div>
<div class="line"><a id="l04602" name="l04602"></a><span class="lineno"> 4602</span>}</div>
<div class="line"><a id="l04603" name="l04603"></a><span class="lineno"> 4603</span></div>
<div class="line"><a id="l04610" name="l04610"></a><span class="lineno"> 4610</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_CC1(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04611" name="l04611"></a><span class="lineno"> 4611</span>{</div>
<div class="line"><a id="l04612" name="l04612"></a><span class="lineno"> 4612</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">TIM_DIER_CC1IE</a>);</div>
<div class="line"><a id="l04613" name="l04613"></a><span class="lineno"> 4613</span>}</div>
<div class="line"><a id="l04614" name="l04614"></a><span class="lineno"> 4614</span></div>
<div class="line"><a id="l04621" name="l04621"></a><span class="lineno"> 4621</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04622" name="l04622"></a><span class="lineno"> 4622</span>{</div>
<div class="line"><a id="l04623" name="l04623"></a><span class="lineno"> 4623</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">TIM_DIER_CC1IE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">TIM_DIER_CC1IE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04624" name="l04624"></a><span class="lineno"> 4624</span>}</div>
<div class="line"><a id="l04625" name="l04625"></a><span class="lineno"> 4625</span></div>
<div class="line"><a id="l04632" name="l04632"></a><span class="lineno"> 4632</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_CC2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04633" name="l04633"></a><span class="lineno"> 4633</span>{</div>
<div class="line"><a id="l04634" name="l04634"></a><span class="lineno"> 4634</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">TIM_DIER_CC2IE</a>);</div>
<div class="line"><a id="l04635" name="l04635"></a><span class="lineno"> 4635</span>}</div>
<div class="line"><a id="l04636" name="l04636"></a><span class="lineno"> 4636</span></div>
<div class="line"><a id="l04643" name="l04643"></a><span class="lineno"> 4643</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_CC2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04644" name="l04644"></a><span class="lineno"> 4644</span>{</div>
<div class="line"><a id="l04645" name="l04645"></a><span class="lineno"> 4645</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">TIM_DIER_CC2IE</a>);</div>
<div class="line"><a id="l04646" name="l04646"></a><span class="lineno"> 4646</span>}</div>
<div class="line"><a id="l04647" name="l04647"></a><span class="lineno"> 4647</span></div>
<div class="line"><a id="l04654" name="l04654"></a><span class="lineno"> 4654</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04655" name="l04655"></a><span class="lineno"> 4655</span>{</div>
<div class="line"><a id="l04656" name="l04656"></a><span class="lineno"> 4656</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">TIM_DIER_CC2IE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">TIM_DIER_CC2IE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04657" name="l04657"></a><span class="lineno"> 4657</span>}</div>
<div class="line"><a id="l04658" name="l04658"></a><span class="lineno"> 4658</span></div>
<div class="line"><a id="l04665" name="l04665"></a><span class="lineno"> 4665</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_CC3(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04666" name="l04666"></a><span class="lineno"> 4666</span>{</div>
<div class="line"><a id="l04667" name="l04667"></a><span class="lineno"> 4667</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">TIM_DIER_CC3IE</a>);</div>
<div class="line"><a id="l04668" name="l04668"></a><span class="lineno"> 4668</span>}</div>
<div class="line"><a id="l04669" name="l04669"></a><span class="lineno"> 4669</span></div>
<div class="line"><a id="l04676" name="l04676"></a><span class="lineno"> 4676</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_CC3(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04677" name="l04677"></a><span class="lineno"> 4677</span>{</div>
<div class="line"><a id="l04678" name="l04678"></a><span class="lineno"> 4678</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">TIM_DIER_CC3IE</a>);</div>
<div class="line"><a id="l04679" name="l04679"></a><span class="lineno"> 4679</span>}</div>
<div class="line"><a id="l04680" name="l04680"></a><span class="lineno"> 4680</span></div>
<div class="line"><a id="l04687" name="l04687"></a><span class="lineno"> 4687</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04688" name="l04688"></a><span class="lineno"> 4688</span>{</div>
<div class="line"><a id="l04689" name="l04689"></a><span class="lineno"> 4689</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">TIM_DIER_CC3IE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">TIM_DIER_CC3IE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04690" name="l04690"></a><span class="lineno"> 4690</span>}</div>
<div class="line"><a id="l04691" name="l04691"></a><span class="lineno"> 4691</span></div>
<div class="line"><a id="l04698" name="l04698"></a><span class="lineno"> 4698</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_CC4(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04699" name="l04699"></a><span class="lineno"> 4699</span>{</div>
<div class="line"><a id="l04700" name="l04700"></a><span class="lineno"> 4700</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">TIM_DIER_CC4IE</a>);</div>
<div class="line"><a id="l04701" name="l04701"></a><span class="lineno"> 4701</span>}</div>
<div class="line"><a id="l04702" name="l04702"></a><span class="lineno"> 4702</span></div>
<div class="line"><a id="l04709" name="l04709"></a><span class="lineno"> 4709</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_CC4(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04710" name="l04710"></a><span class="lineno"> 4710</span>{</div>
<div class="line"><a id="l04711" name="l04711"></a><span class="lineno"> 4711</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">TIM_DIER_CC4IE</a>);</div>
<div class="line"><a id="l04712" name="l04712"></a><span class="lineno"> 4712</span>}</div>
<div class="line"><a id="l04713" name="l04713"></a><span class="lineno"> 4713</span></div>
<div class="line"><a id="l04720" name="l04720"></a><span class="lineno"> 4720</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04721" name="l04721"></a><span class="lineno"> 4721</span>{</div>
<div class="line"><a id="l04722" name="l04722"></a><span class="lineno"> 4722</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">TIM_DIER_CC4IE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">TIM_DIER_CC4IE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04723" name="l04723"></a><span class="lineno"> 4723</span>}</div>
<div class="line"><a id="l04724" name="l04724"></a><span class="lineno"> 4724</span></div>
<div class="line"><a id="l04731" name="l04731"></a><span class="lineno"> 4731</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_COM(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04732" name="l04732"></a><span class="lineno"> 4732</span>{</div>
<div class="line"><a id="l04733" name="l04733"></a><span class="lineno"> 4733</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">TIM_DIER_COMIE</a>);</div>
<div class="line"><a id="l04734" name="l04734"></a><span class="lineno"> 4734</span>}</div>
<div class="line"><a id="l04735" name="l04735"></a><span class="lineno"> 4735</span></div>
<div class="line"><a id="l04742" name="l04742"></a><span class="lineno"> 4742</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_COM(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04743" name="l04743"></a><span class="lineno"> 4743</span>{</div>
<div class="line"><a id="l04744" name="l04744"></a><span class="lineno"> 4744</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">TIM_DIER_COMIE</a>);</div>
<div class="line"><a id="l04745" name="l04745"></a><span class="lineno"> 4745</span>}</div>
<div class="line"><a id="l04746" name="l04746"></a><span class="lineno"> 4746</span></div>
<div class="line"><a id="l04753" name="l04753"></a><span class="lineno"> 4753</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04754" name="l04754"></a><span class="lineno"> 4754</span>{</div>
<div class="line"><a id="l04755" name="l04755"></a><span class="lineno"> 4755</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">TIM_DIER_COMIE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">TIM_DIER_COMIE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04756" name="l04756"></a><span class="lineno"> 4756</span>}</div>
<div class="line"><a id="l04757" name="l04757"></a><span class="lineno"> 4757</span></div>
<div class="line"><a id="l04764" name="l04764"></a><span class="lineno"> 4764</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_TRIG(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04765" name="l04765"></a><span class="lineno"> 4765</span>{</div>
<div class="line"><a id="l04766" name="l04766"></a><span class="lineno"> 4766</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">TIM_DIER_TIE</a>);</div>
<div class="line"><a id="l04767" name="l04767"></a><span class="lineno"> 4767</span>}</div>
<div class="line"><a id="l04768" name="l04768"></a><span class="lineno"> 4768</span></div>
<div class="line"><a id="l04775" name="l04775"></a><span class="lineno"> 4775</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_TRIG(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04776" name="l04776"></a><span class="lineno"> 4776</span>{</div>
<div class="line"><a id="l04777" name="l04777"></a><span class="lineno"> 4777</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">TIM_DIER_TIE</a>);</div>
<div class="line"><a id="l04778" name="l04778"></a><span class="lineno"> 4778</span>}</div>
<div class="line"><a id="l04779" name="l04779"></a><span class="lineno"> 4779</span></div>
<div class="line"><a id="l04786" name="l04786"></a><span class="lineno"> 4786</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04787" name="l04787"></a><span class="lineno"> 4787</span>{</div>
<div class="line"><a id="l04788" name="l04788"></a><span class="lineno"> 4788</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">TIM_DIER_TIE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">TIM_DIER_TIE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04789" name="l04789"></a><span class="lineno"> 4789</span>}</div>
<div class="line"><a id="l04790" name="l04790"></a><span class="lineno"> 4790</span></div>
<div class="line"><a id="l04797" name="l04797"></a><span class="lineno"> 4797</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableIT_BRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04798" name="l04798"></a><span class="lineno"> 4798</span>{</div>
<div class="line"><a id="l04799" name="l04799"></a><span class="lineno"> 4799</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">TIM_DIER_BIE</a>);</div>
<div class="line"><a id="l04800" name="l04800"></a><span class="lineno"> 4800</span>}</div>
<div class="line"><a id="l04801" name="l04801"></a><span class="lineno"> 4801</span></div>
<div class="line"><a id="l04808" name="l04808"></a><span class="lineno"> 4808</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableIT_BRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04809" name="l04809"></a><span class="lineno"> 4809</span>{</div>
<div class="line"><a id="l04810" name="l04810"></a><span class="lineno"> 4810</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">TIM_DIER_BIE</a>);</div>
<div class="line"><a id="l04811" name="l04811"></a><span class="lineno"> 4811</span>}</div>
<div class="line"><a id="l04812" name="l04812"></a><span class="lineno"> 4812</span></div>
<div class="line"><a id="l04819" name="l04819"></a><span class="lineno"> 4819</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04820" name="l04820"></a><span class="lineno"> 4820</span>{</div>
<div class="line"><a id="l04821" name="l04821"></a><span class="lineno"> 4821</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">TIM_DIER_BIE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">TIM_DIER_BIE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04822" name="l04822"></a><span class="lineno"> 4822</span>}</div>
<div class="line"><a id="l04823" name="l04823"></a><span class="lineno"> 4823</span></div>
<div class="line"><a id="l04827" name="l04827"></a><span class="lineno"> 4827</span></div>
<div class="line"><a id="l04837" name="l04837"></a><span class="lineno"> 4837</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableDMAReq_UPDATE(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04838" name="l04838"></a><span class="lineno"> 4838</span>{</div>
<div class="line"><a id="l04839" name="l04839"></a><span class="lineno"> 4839</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">TIM_DIER_UDE</a>);</div>
<div class="line"><a id="l04840" name="l04840"></a><span class="lineno"> 4840</span>}</div>
<div class="line"><a id="l04841" name="l04841"></a><span class="lineno"> 4841</span></div>
<div class="line"><a id="l04848" name="l04848"></a><span class="lineno"> 4848</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableDMAReq_UPDATE(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04849" name="l04849"></a><span class="lineno"> 4849</span>{</div>
<div class="line"><a id="l04850" name="l04850"></a><span class="lineno"> 4850</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">TIM_DIER_UDE</a>);</div>
<div class="line"><a id="l04851" name="l04851"></a><span class="lineno"> 4851</span>}</div>
<div class="line"><a id="l04852" name="l04852"></a><span class="lineno"> 4852</span></div>
<div class="line"><a id="l04859" name="l04859"></a><span class="lineno"> 4859</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04860" name="l04860"></a><span class="lineno"> 4860</span>{</div>
<div class="line"><a id="l04861" name="l04861"></a><span class="lineno"> 4861</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">TIM_DIER_UDE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">TIM_DIER_UDE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04862" name="l04862"></a><span class="lineno"> 4862</span>}</div>
<div class="line"><a id="l04863" name="l04863"></a><span class="lineno"> 4863</span></div>
<div class="line"><a id="l04870" name="l04870"></a><span class="lineno"> 4870</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableDMAReq_CC1(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04871" name="l04871"></a><span class="lineno"> 4871</span>{</div>
<div class="line"><a id="l04872" name="l04872"></a><span class="lineno"> 4872</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">TIM_DIER_CC1DE</a>);</div>
<div class="line"><a id="l04873" name="l04873"></a><span class="lineno"> 4873</span>}</div>
<div class="line"><a id="l04874" name="l04874"></a><span class="lineno"> 4874</span></div>
<div class="line"><a id="l04881" name="l04881"></a><span class="lineno"> 4881</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableDMAReq_CC1(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04882" name="l04882"></a><span class="lineno"> 4882</span>{</div>
<div class="line"><a id="l04883" name="l04883"></a><span class="lineno"> 4883</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">TIM_DIER_CC1DE</a>);</div>
<div class="line"><a id="l04884" name="l04884"></a><span class="lineno"> 4884</span>}</div>
<div class="line"><a id="l04885" name="l04885"></a><span class="lineno"> 4885</span></div>
<div class="line"><a id="l04892" name="l04892"></a><span class="lineno"> 4892</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04893" name="l04893"></a><span class="lineno"> 4893</span>{</div>
<div class="line"><a id="l04894" name="l04894"></a><span class="lineno"> 4894</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">TIM_DIER_CC1DE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">TIM_DIER_CC1DE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04895" name="l04895"></a><span class="lineno"> 4895</span>}</div>
<div class="line"><a id="l04896" name="l04896"></a><span class="lineno"> 4896</span></div>
<div class="line"><a id="l04903" name="l04903"></a><span class="lineno"> 4903</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableDMAReq_CC2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04904" name="l04904"></a><span class="lineno"> 4904</span>{</div>
<div class="line"><a id="l04905" name="l04905"></a><span class="lineno"> 4905</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">TIM_DIER_CC2DE</a>);</div>
<div class="line"><a id="l04906" name="l04906"></a><span class="lineno"> 4906</span>}</div>
<div class="line"><a id="l04907" name="l04907"></a><span class="lineno"> 4907</span></div>
<div class="line"><a id="l04914" name="l04914"></a><span class="lineno"> 4914</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableDMAReq_CC2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04915" name="l04915"></a><span class="lineno"> 4915</span>{</div>
<div class="line"><a id="l04916" name="l04916"></a><span class="lineno"> 4916</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">TIM_DIER_CC2DE</a>);</div>
<div class="line"><a id="l04917" name="l04917"></a><span class="lineno"> 4917</span>}</div>
<div class="line"><a id="l04918" name="l04918"></a><span class="lineno"> 4918</span></div>
<div class="line"><a id="l04925" name="l04925"></a><span class="lineno"> 4925</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04926" name="l04926"></a><span class="lineno"> 4926</span>{</div>
<div class="line"><a id="l04927" name="l04927"></a><span class="lineno"> 4927</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">TIM_DIER_CC2DE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">TIM_DIER_CC2DE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04928" name="l04928"></a><span class="lineno"> 4928</span>}</div>
<div class="line"><a id="l04929" name="l04929"></a><span class="lineno"> 4929</span></div>
<div class="line"><a id="l04936" name="l04936"></a><span class="lineno"> 4936</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableDMAReq_CC3(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04937" name="l04937"></a><span class="lineno"> 4937</span>{</div>
<div class="line"><a id="l04938" name="l04938"></a><span class="lineno"> 4938</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">TIM_DIER_CC3DE</a>);</div>
<div class="line"><a id="l04939" name="l04939"></a><span class="lineno"> 4939</span>}</div>
<div class="line"><a id="l04940" name="l04940"></a><span class="lineno"> 4940</span></div>
<div class="line"><a id="l04947" name="l04947"></a><span class="lineno"> 4947</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableDMAReq_CC3(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04948" name="l04948"></a><span class="lineno"> 4948</span>{</div>
<div class="line"><a id="l04949" name="l04949"></a><span class="lineno"> 4949</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">TIM_DIER_CC3DE</a>);</div>
<div class="line"><a id="l04950" name="l04950"></a><span class="lineno"> 4950</span>}</div>
<div class="line"><a id="l04951" name="l04951"></a><span class="lineno"> 4951</span></div>
<div class="line"><a id="l04958" name="l04958"></a><span class="lineno"> 4958</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04959" name="l04959"></a><span class="lineno"> 4959</span>{</div>
<div class="line"><a id="l04960" name="l04960"></a><span class="lineno"> 4960</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">TIM_DIER_CC3DE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">TIM_DIER_CC3DE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04961" name="l04961"></a><span class="lineno"> 4961</span>}</div>
<div class="line"><a id="l04962" name="l04962"></a><span class="lineno"> 4962</span></div>
<div class="line"><a id="l04969" name="l04969"></a><span class="lineno"> 4969</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableDMAReq_CC4(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04970" name="l04970"></a><span class="lineno"> 4970</span>{</div>
<div class="line"><a id="l04971" name="l04971"></a><span class="lineno"> 4971</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">TIM_DIER_CC4DE</a>);</div>
<div class="line"><a id="l04972" name="l04972"></a><span class="lineno"> 4972</span>}</div>
<div class="line"><a id="l04973" name="l04973"></a><span class="lineno"> 4973</span></div>
<div class="line"><a id="l04980" name="l04980"></a><span class="lineno"> 4980</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableDMAReq_CC4(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04981" name="l04981"></a><span class="lineno"> 4981</span>{</div>
<div class="line"><a id="l04982" name="l04982"></a><span class="lineno"> 4982</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">TIM_DIER_CC4DE</a>);</div>
<div class="line"><a id="l04983" name="l04983"></a><span class="lineno"> 4983</span>}</div>
<div class="line"><a id="l04984" name="l04984"></a><span class="lineno"> 4984</span></div>
<div class="line"><a id="l04991" name="l04991"></a><span class="lineno"> 4991</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l04992" name="l04992"></a><span class="lineno"> 4992</span>{</div>
<div class="line"><a id="l04993" name="l04993"></a><span class="lineno"> 4993</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">TIM_DIER_CC4DE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">TIM_DIER_CC4DE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l04994" name="l04994"></a><span class="lineno"> 4994</span>}</div>
<div class="line"><a id="l04995" name="l04995"></a><span class="lineno"> 4995</span></div>
<div class="line"><a id="l05002" name="l05002"></a><span class="lineno"> 5002</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableDMAReq_COM(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05003" name="l05003"></a><span class="lineno"> 5003</span>{</div>
<div class="line"><a id="l05004" name="l05004"></a><span class="lineno"> 5004</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">TIM_DIER_COMDE</a>);</div>
<div class="line"><a id="l05005" name="l05005"></a><span class="lineno"> 5005</span>}</div>
<div class="line"><a id="l05006" name="l05006"></a><span class="lineno"> 5006</span></div>
<div class="line"><a id="l05013" name="l05013"></a><span class="lineno"> 5013</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableDMAReq_COM(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05014" name="l05014"></a><span class="lineno"> 5014</span>{</div>
<div class="line"><a id="l05015" name="l05015"></a><span class="lineno"> 5015</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">TIM_DIER_COMDE</a>);</div>
<div class="line"><a id="l05016" name="l05016"></a><span class="lineno"> 5016</span>}</div>
<div class="line"><a id="l05017" name="l05017"></a><span class="lineno"> 5017</span></div>
<div class="line"><a id="l05024" name="l05024"></a><span class="lineno"> 5024</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05025" name="l05025"></a><span class="lineno"> 5025</span>{</div>
<div class="line"><a id="l05026" name="l05026"></a><span class="lineno"> 5026</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">TIM_DIER_COMDE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">TIM_DIER_COMDE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l05027" name="l05027"></a><span class="lineno"> 5027</span>}</div>
<div class="line"><a id="l05028" name="l05028"></a><span class="lineno"> 5028</span></div>
<div class="line"><a id="l05035" name="l05035"></a><span class="lineno"> 5035</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_EnableDMAReq_TRIG(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05036" name="l05036"></a><span class="lineno"> 5036</span>{</div>
<div class="line"><a id="l05037" name="l05037"></a><span class="lineno"> 5037</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">TIM_DIER_TDE</a>);</div>
<div class="line"><a id="l05038" name="l05038"></a><span class="lineno"> 5038</span>}</div>
<div class="line"><a id="l05039" name="l05039"></a><span class="lineno"> 5039</span></div>
<div class="line"><a id="l05046" name="l05046"></a><span class="lineno"> 5046</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_DisableDMAReq_TRIG(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05047" name="l05047"></a><span class="lineno"> 5047</span>{</div>
<div class="line"><a id="l05048" name="l05048"></a><span class="lineno"> 5048</span>  CLEAR_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">TIM_DIER_TDE</a>);</div>
<div class="line"><a id="l05049" name="l05049"></a><span class="lineno"> 5049</span>}</div>
<div class="line"><a id="l05050" name="l05050"></a><span class="lineno"> 5050</span></div>
<div class="line"><a id="l05057" name="l05057"></a><span class="lineno"> 5057</span>__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05058" name="l05058"></a><span class="lineno"> 5058</span>{</div>
<div class="line"><a id="l05059" name="l05059"></a><span class="lineno"> 5059</span>  <span class="keywordflow">return</span> ((READ_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">DIER</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">TIM_DIER_TDE</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">TIM_DIER_TDE</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l05060" name="l05060"></a><span class="lineno"> 5060</span>}</div>
<div class="line"><a id="l05061" name="l05061"></a><span class="lineno"> 5061</span></div>
<div class="line"><a id="l05065" name="l05065"></a><span class="lineno"> 5065</span></div>
<div class="line"><a id="l05075" name="l05075"></a><span class="lineno"> 5075</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_UPDATE(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05076" name="l05076"></a><span class="lineno"> 5076</span>{</div>
<div class="line"><a id="l05077" name="l05077"></a><span class="lineno"> 5077</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga16f52a8e9aad153223405b965566ae91">TIM_EGR_UG</a>);</div>
<div class="line"><a id="l05078" name="l05078"></a><span class="lineno"> 5078</span>}</div>
<div class="line"><a id="l05079" name="l05079"></a><span class="lineno"> 5079</span></div>
<div class="line"><a id="l05086" name="l05086"></a><span class="lineno"> 5086</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_CC1(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05087" name="l05087"></a><span class="lineno"> 5087</span>{</div>
<div class="line"><a id="l05088" name="l05088"></a><span class="lineno"> 5088</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0a1318609761df5de5213e9e75b5aa6a">TIM_EGR_CC1G</a>);</div>
<div class="line"><a id="l05089" name="l05089"></a><span class="lineno"> 5089</span>}</div>
<div class="line"><a id="l05090" name="l05090"></a><span class="lineno"> 5090</span></div>
<div class="line"><a id="l05097" name="l05097"></a><span class="lineno"> 5097</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_CC2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05098" name="l05098"></a><span class="lineno"> 5098</span>{</div>
<div class="line"><a id="l05099" name="l05099"></a><span class="lineno"> 5099</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5423de00e86aeb8a4657a509af485055">TIM_EGR_CC2G</a>);</div>
<div class="line"><a id="l05100" name="l05100"></a><span class="lineno"> 5100</span>}</div>
<div class="line"><a id="l05101" name="l05101"></a><span class="lineno"> 5101</span></div>
<div class="line"><a id="l05108" name="l05108"></a><span class="lineno"> 5108</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_CC3(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05109" name="l05109"></a><span class="lineno"> 5109</span>{</div>
<div class="line"><a id="l05110" name="l05110"></a><span class="lineno"> 5110</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga064d2030abccc099ded418fd81d6aa07">TIM_EGR_CC3G</a>);</div>
<div class="line"><a id="l05111" name="l05111"></a><span class="lineno"> 5111</span>}</div>
<div class="line"><a id="l05112" name="l05112"></a><span class="lineno"> 5112</span></div>
<div class="line"><a id="l05119" name="l05119"></a><span class="lineno"> 5119</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_CC4(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05120" name="l05120"></a><span class="lineno"> 5120</span>{</div>
<div class="line"><a id="l05121" name="l05121"></a><span class="lineno"> 5121</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1c4e5555dd3be8ab1e631d1053f4a305">TIM_EGR_CC4G</a>);</div>
<div class="line"><a id="l05122" name="l05122"></a><span class="lineno"> 5122</span>}</div>
<div class="line"><a id="l05123" name="l05123"></a><span class="lineno"> 5123</span></div>
<div class="line"><a id="l05130" name="l05130"></a><span class="lineno"> 5130</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_COM(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05131" name="l05131"></a><span class="lineno"> 5131</span>{</div>
<div class="line"><a id="l05132" name="l05132"></a><span class="lineno"> 5132</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadb06f8bb364307695c7d6a028391de7b">TIM_EGR_COMG</a>);</div>
<div class="line"><a id="l05133" name="l05133"></a><span class="lineno"> 5133</span>}</div>
<div class="line"><a id="l05134" name="l05134"></a><span class="lineno"> 5134</span></div>
<div class="line"><a id="l05141" name="l05141"></a><span class="lineno"> 5141</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_TRIG(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05142" name="l05142"></a><span class="lineno"> 5142</span>{</div>
<div class="line"><a id="l05143" name="l05143"></a><span class="lineno"> 5143</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga2eabface433d6adaa2dee3df49852585">TIM_EGR_TG</a>);</div>
<div class="line"><a id="l05144" name="l05144"></a><span class="lineno"> 5144</span>}</div>
<div class="line"><a id="l05145" name="l05145"></a><span class="lineno"> 5145</span></div>
<div class="line"><a id="l05152" name="l05152"></a><span class="lineno"> 5152</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_BRK(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05153" name="l05153"></a><span class="lineno"> 5153</span>{</div>
<div class="line"><a id="l05154" name="l05154"></a><span class="lineno"> 5154</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga08c5635a0ac0ce5618485319a4fa0f18">TIM_EGR_BG</a>);</div>
<div class="line"><a id="l05155" name="l05155"></a><span class="lineno"> 5155</span>}</div>
<div class="line"><a id="l05156" name="l05156"></a><span class="lineno"> 5156</span></div>
<div class="line"><a id="l05163" name="l05163"></a><span class="lineno"> 5163</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_TIM_GenerateEvent_BRK2(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx)</div>
<div class="line"><a id="l05164" name="l05164"></a><span class="lineno"> 5164</span>{</div>
<div class="line"><a id="l05165" name="l05165"></a><span class="lineno"> 5165</span>  SET_BIT(TIMx-&gt;<a class="code hl_variable" href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">EGR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga42a7335ccbf7565d45b3efd51c213af2">TIM_EGR_B2G</a>);</div>
<div class="line"><a id="l05166" name="l05166"></a><span class="lineno"> 5166</span>}</div>
<div class="line"><a id="l05167" name="l05167"></a><span class="lineno"> 5167</span></div>
<div class="line"><a id="l05171" name="l05171"></a><span class="lineno"> 5171</span> </div>
<div class="line"><a id="l05172" name="l05172"></a><span class="lineno"> 5172</span><span class="preprocessor">#if defined(USE_FULL_LL_DRIVER)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l05176" name="l05176"></a><span class="lineno"> 5176</span> </div>
<div class="line"><a id="l05177" name="l05177"></a><span class="lineno"> 5177</span>ErrorStatus LL_TIM_DeInit(<span class="keyword">const</span> <a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx);</div>
<div class="line"><a id="l05178" name="l05178"></a><span class="lineno"> 5178</span><span class="keywordtype">void</span> LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);</div>
<div class="line"><a id="l05179" name="l05179"></a><span class="lineno"> 5179</span>ErrorStatus LL_TIM_Init(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, <span class="keyword">const</span> LL_TIM_InitTypeDef *TIM_InitStruct);</div>
<div class="line"><a id="l05180" name="l05180"></a><span class="lineno"> 5180</span><span class="keywordtype">void</span> LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);</div>
<div class="line"><a id="l05181" name="l05181"></a><span class="lineno"> 5181</span>ErrorStatus LL_TIM_OC_Init(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, <span class="keyword">const</span> LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);</div>
<div class="line"><a id="l05182" name="l05182"></a><span class="lineno"> 5182</span><span class="keywordtype">void</span> LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);</div>
<div class="line"><a id="l05183" name="l05183"></a><span class="lineno"> 5183</span>ErrorStatus LL_TIM_IC_Init(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, uint32_t Channel, <span class="keyword">const</span> LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);</div>
<div class="line"><a id="l05184" name="l05184"></a><span class="lineno"> 5184</span><span class="keywordtype">void</span> LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);</div>
<div class="line"><a id="l05185" name="l05185"></a><span class="lineno"> 5185</span>ErrorStatus LL_TIM_ENCODER_Init(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, <span class="keyword">const</span> LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);</div>
<div class="line"><a id="l05186" name="l05186"></a><span class="lineno"> 5186</span><span class="keywordtype">void</span> LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);</div>
<div class="line"><a id="l05187" name="l05187"></a><span class="lineno"> 5187</span>ErrorStatus LL_TIM_HALLSENSOR_Init(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, <span class="keyword">const</span> LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);</div>
<div class="line"><a id="l05188" name="l05188"></a><span class="lineno"> 5188</span><span class="keywordtype">void</span> LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);</div>
<div class="line"><a id="l05189" name="l05189"></a><span class="lineno"> 5189</span>ErrorStatus LL_TIM_BDTR_Init(<a class="code hl_struct" href="struct_t_i_m___type_def.html">TIM_TypeDef</a> *TIMx, <span class="keyword">const</span> LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);</div>
<div class="line"><a id="l05193" name="l05193"></a><span class="lineno"> 5193</span><span class="preprocessor">#endif </span><span class="comment">/* USE_FULL_LL_DRIVER */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l05194" name="l05194"></a><span class="lineno"> 5194</span></div>
<div class="line"><a id="l05198" name="l05198"></a><span class="lineno"> 5198</span></div>
<div class="line"><a id="l05202" name="l05202"></a><span class="lineno"> 5202</span> </div>
<div class="line"><a id="l05203" name="l05203"></a><span class="lineno"> 5203</span><span class="preprocessor">#endif </span><span class="comment">/* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17  || TIM23  || TIM24 */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l05204" name="l05204"></a><span class="lineno"> 5204</span></div>
<div class="line"><a id="l05208" name="l05208"></a><span class="lineno"> 5208</span> </div>
<div class="line"><a id="l05209" name="l05209"></a><span class="lineno"> 5209</span><span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a id="l05210" name="l05210"></a><span class="lineno"> 5210</span>}</div>
<div class="line"><a id="l05211" name="l05211"></a><span class="lineno"> 5211</span><span class="preprocessor">#endif</span></div>
<div class="line"><a id="l05212" name="l05212"></a><span class="lineno"> 5212</span> </div>
<div class="line"><a id="l05213" name="l05213"></a><span class="lineno"> 5213</span><span class="preprocessor">#endif </span><span class="comment">/* __STM32H7xx_LL_TIM_H */</span><span class="preprocessor"></span></div>
<div class="ttc" id="acore__armv81mml_8h_html_aec43007d9998a0a0e01faede4133d6be"><div class="ttname"><a href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a></div><div class="ttdeci">#define __IO</div><div class="ttdef"><b>Definition</b> core_armv81mml.h:277</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga064d2030abccc099ded418fd81d6aa07"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga064d2030abccc099ded418fd81d6aa07">TIM_EGR_CC3G</a></div><div class="ttdeci">#define TIM_EGR_CC3G</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19614</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga06c997c2c23e8bef7ca07579762c113b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b">TIM_CR1_URS</a></div><div class="ttdeci">#define TIM_CR1_URS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19377</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga08c5635a0ac0ce5618485319a4fa0f18"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga08c5635a0ac0ce5618485319a4fa0f18">TIM_EGR_BG</a></div><div class="ttdeci">#define TIM_EGR_BG</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19626</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0a1318609761df5de5213e9e75b5aa6a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0a1318609761df5de5213e9e75b5aa6a">TIM_EGR_CC1G</a></div><div class="ttdeci">#define TIM_EGR_CC1G</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19608</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0ca0aedba14241caff739afb3c3ee291"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291">TIM_CCER_CC1P</a></div><div class="ttdeci">#define TIM_CCER_CC1P</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19800</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0ebb9e631876435e276211d88e797386"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0ebb9e631876435e276211d88e797386">TIM_SMCR_ETPS</a></div><div class="ttdeci">#define TIM_SMCR_ETPS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19494</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga1567bff5dc0564b26a8b3cff1f0fe0a4"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4">TIM_DIER_CC3DE</a></div><div class="ttdeci">#define TIM_DIER_CC3DE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19541</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga16f52a8e9aad153223405b965566ae91"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga16f52a8e9aad153223405b965566ae91">TIM_EGR_UG</a></div><div class="ttdeci">#define TIM_EGR_UG</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19605</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga1aa54ddf87a4b339881a8d5368ec80eb"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb">TIM_CCMR1_OC1PE</a></div><div class="ttdeci">#define TIM_CCMR1_OC1PE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19644</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga1ba7f7ca97eeaf6cc23cd6765c6bf678"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678">TIM_DIER_CC1IE</a></div><div class="ttdeci">#define TIM_DIER_CC1IE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19511</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga1c4e5555dd3be8ab1e631d1053f4a305"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga1c4e5555dd3be8ab1e631d1053f4a305">TIM_EGR_CC4G</a></div><div class="ttdeci">#define TIM_EGR_CC4G</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19617</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga1fcb0d6d9fb7486a5901032fd81aef6a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a">TIM_DIER_BIE</a></div><div class="ttdeci">#define TIM_DIER_BIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19529</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga2167773377ba03c863cc49342c67789f"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga2167773377ba03c863cc49342c67789f">TIM_SR_CC5IF</a></div><div class="ttdeci">#define TIM_SR_CC5IF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19594</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga25a48bf099467169aa50464fbf462bd8"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8">TIM_SR_CC2IF</a></div><div class="ttdeci">#define TIM_SR_CC2IF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19561</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga277a096614829feba2d0a4fbb7d3dffc"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc">TIM_BDTR_MOE</a></div><div class="ttdeci">#define TIM_BDTR_MOE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19949</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga2a5f335c3d7a4f82d1e91dc1511e3322"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga2a5f335c3d7a4f82d1e91dc1511e3322">TIM_SMCR_ETP</a></div><div class="ttdeci">#define TIM_SMCR_ETP</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19503</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga2eabface433d6adaa2dee3df49852585"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga2eabface433d6adaa2dee3df49852585">TIM_EGR_TG</a></div><div class="ttdeci">#define TIM_EGR_TG</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19623</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga2ed336e59081fe830617f97dcb71678b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga2ed336e59081fe830617f97dcb71678b">TIM_BDTR_BKDSRM</a></div><div class="ttdeci">#define TIM_BDTR_BKDSRM</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19966</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga31b26bf058f88d771c33aff85ec89358"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358">TIM_CR2_OIS1</a></div><div class="ttdeci">#define TIM_CR2_OIS1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19428</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga3247abbbf0d00260be051d176d88020e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e">TIM_BDTR_BKP</a></div><div class="ttdeci">#define TIM_BDTR_BKP</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19943</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga331a1d5f39d5f47b5409054e693fc651"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651">TIM_SMCR_ECE</a></div><div class="ttdeci">#define TIM_SMCR_ECE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19500</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga352b3c389bde13dd6049de0afdd874f1"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1">TIM_CR1_CMS</a></div><div class="ttdeci">#define TIM_CR1_CMS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19387</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga3b7798da5863d559ea9a642af6658050"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050">TIM_SR_CC2OF</a></div><div class="ttdeci">#define TIM_SR_CC2OF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19585</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga403fc501d4d8de6cabee6b07acb81a36"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36">TIM_CCER_CC1NP</a></div><div class="ttdeci">#define TIM_CCER_CC1NP</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19806</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga42a7335ccbf7565d45b3efd51c213af2"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga42a7335ccbf7565d45b3efd51c213af2">TIM_EGR_B2G</a></div><div class="ttdeci">#define TIM_EGR_B2G</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19629</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga449a61344a97608d85384c29f003c0e9"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9">TIM_SR_CC1IF</a></div><div class="ttdeci">#define TIM_SR_CC1IF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19558</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga4a3ad409f6b147cdcbafbfe29102f3fd"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd">TIM_CR1_ARPE</a></div><div class="ttdeci">#define TIM_CR1_ARPE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19393</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga4edf003f04bcf250bddf5ed284201c2e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e">TIM_DIER_CC3IE</a></div><div class="ttdeci">#define TIM_DIER_CC3IE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19517</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga50aff10d1577a94de8c4aa46cd2cbdb5"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga50aff10d1577a94de8c4aa46cd2cbdb5">TIM_BDTR_BK2E</a></div><div class="ttdeci">#define TIM_BDTR_BK2E</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19960</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5168e7f269c569c733b656bb86b5c3a5"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5168e7f269c569c733b656bb86b5c3a5">TIM_TISEL_TI1SEL</a></div><div class="ttdeci">#define TIM_TISEL_TI1SEL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:20096</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga52101db4ca2c7b3003f1b16a49b2032c"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c">TIM_SMCR_MSM</a></div><div class="ttdeci">#define TIM_SMCR_MSM</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19482</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5423de00e86aeb8a4657a509af485055"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5423de00e86aeb8a4657a509af485055">TIM_EGR_CC2G</a></div><div class="ttdeci">#define TIM_EGR_CC2G</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19611</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga57a4e24f3276f4c908874940657dc7e7"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga57a4e24f3276f4c908874940657dc7e7">TIM_CCR5_CCR5</a></div><div class="ttdeci">#define TIM_CCR5_CCR5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19897</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga58c65231de95b67cb2d115064ab57f60"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga58c65231de95b67cb2d115064ab57f60">TIM_BDTR_BKBID</a></div><div class="ttdeci">#define TIM_BDTR_BKBID</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19972</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga58f97064991095b28c91028ca3cca28e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e">TIM_DIER_CC2DE</a></div><div class="ttdeci">#define TIM_DIER_CC2DE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19538</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga59f15008050f91fa3ecc9eaaa971a509"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509">TIM_BDTR_AOE</a></div><div class="ttdeci">#define TIM_BDTR_AOE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19946</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5a752d4295f100708df9b8be5a7f439d"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d">TIM_DIER_TDE</a></div><div class="ttdeci">#define TIM_DIER_TDE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19550</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5c6d3e0495e6c06da4bdd0ad8995a32b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b">TIM_DIER_UIE</a></div><div class="ttdeci">#define TIM_DIER_UIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19508</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga66b51c31aab6f353303cffb10593a027"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga66b51c31aab6f353303cffb10593a027">TIM_CCR5_GC5C2</a></div><div class="ttdeci">#define TIM_CCR5_GC5C2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19903</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6ad0f562a014572793b49fe87184338b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b">TIM_DIER_CC4IE</a></div><div class="ttdeci">#define TIM_DIER_CC4IE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19520</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6d3d1488296350af6d36fbbf71905d29"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6d3d1488296350af6d36fbbf71905d29">TIM_CR1_OPM</a></div><div class="ttdeci">#define TIM_CR1_OPM</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19380</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6d52cd5a57c9a26b0d993c93d9875097"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097">TIM_SR_BIF</a></div><div class="ttdeci">#define TIM_SR_BIF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19576</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6ddb3dc889733e71d812baa3873cb13b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">TIM_CCMR1_OC1M</a></div><div class="ttdeci">#define TIM_CCMR1_OC1M</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19648</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga74250b040dd9fd9c09dcc54cdd6d86d8"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8">TIM_BDTR_BKE</a></div><div class="ttdeci">#define TIM_BDTR_BKE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19940</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga757c59b690770adebf33e20d3d9dec15"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15">TIM_DIER_CC2IE</a></div><div class="ttdeci">#define TIM_DIER_CC2IE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19514</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga759883f669298c750d8dbf3d2fd2fab2"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga759883f669298c750d8dbf3d2fd2fab2">TIM_BDTR_BK2DSRM</a></div><div class="ttdeci">#define TIM_BDTR_BK2DSRM</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19969</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga79c3fab9d33de953a0a7f7d6516c73bc"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc">TIM_DIER_COMDE</a></div><div class="ttdeci">#define TIM_DIER_COMDE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19547</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7c19a6840ec57afc1b9ae48703f60fc1"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7c19a6840ec57afc1b9ae48703f60fc1">TIM_TISEL_TI3SEL</a></div><div class="ttdeci">#define TIM_TISEL_TI3SEL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:20112</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7c8b16f3ced6ec03e9001276b134846e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e">TIM_SR_TIF</a></div><div class="ttdeci">#define TIM_SR_TIF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19573</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7e4215d17f0548dfcf0b15fe4d0f4651"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7e4215d17f0548dfcf0b15fe4d0f4651">TIM_BDTR_LOCK</a></div><div class="ttdeci">#define TIM_BDTR_LOCK</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19928</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7eff9d6247daaa7bdbd6f009ab80d595"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7eff9d6247daaa7bdbd6f009ab80d595">TIM_TISEL_TI4SEL</a></div><div class="ttdeci">#define TIM_TISEL_TI4SEL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:20120</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga819c4b27f8fa99b537c4407521f9780c"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c">TIM_SR_CC1OF</a></div><div class="ttdeci">#define TIM_SR_CC1OF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19582</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga81ba979e8309b66808e06e4de34bc740"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740">TIM_SR_CC4OF</a></div><div class="ttdeci">#define TIM_SR_CC4OF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19591</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga8680e719bca2b672d850504220ae51fc"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga8680e719bca2b672d850504220ae51fc">TIM_SMCR_TS</a></div><div class="ttdeci">#define TIM_SMCR_TS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19473</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga8f44c50cf9928d2afab014e2ca29baba"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba">TIM_CCMR1_OC1CE</a></div><div class="ttdeci">#define TIM_CCMR1_OC1CE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19656</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga9060f1ca4c5df1ab6e70af699ac71a16"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga9060f1ca4c5df1ab6e70af699ac71a16">TIM_CNT_UIFCPY</a></div><div class="ttdeci">#define TIM_CNT_UIFCPY</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19858</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga91775c029171c4585e9cca6ebf1cd57a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a">TIM_SR_COMIF</a></div><div class="ttdeci">#define TIM_SR_COMIF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19570</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga93d86355e5e3b399ed45e1ca83abed2a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a">TIM_CR1_CEN</a></div><div class="ttdeci">#define TIM_CR1_CEN</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19371</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga94911ade52aef76f5ad41613f9fc9590"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga94911ade52aef76f5ad41613f9fc9590">TIM_BDTR_BK2P</a></div><div class="ttdeci">#define TIM_BDTR_BK2P</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19963</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga95291df1eaf532c5c996d176648938eb"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb">TIM_CCMR1_CC1S</a></div><div class="ttdeci">#define TIM_CCMR1_CC1S</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19635</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaa4f2a9f0cf7b60e3c623af451f141f3c"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c">TIM_CR1_UDIS</a></div><div class="ttdeci">#define TIM_CR1_UDIS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19374</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaa755fef2c4e96c63f2ea1cd9a32f956a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a">TIM_DIER_TIE</a></div><div class="ttdeci">#define TIM_DIER_TIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19526</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaaa6987d980e5c4c71c7d0faa1eb97a45"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaaa6987d980e5c4c71c7d0faa1eb97a45">TIM_CR2_MMS</a></div><div class="ttdeci">#define TIM_CR2_MMS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19418</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaaaf84ef0edc60a2bb1d724fd28ae522e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaaaf84ef0edc60a2bb1d724fd28ae522e">TIM_CCR5_GC5C3</a></div><div class="ttdeci">#define TIM_CCR5_GC5C3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19906</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaaba034412c54fa07024e516492748614"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614">TIM_DIER_CC4DE</a></div><div class="ttdeci">#define TIM_DIER_CC4DE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19544</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaae22c9c1197107d6fa629f419a29541e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e">TIM_CR2_CCPC</a></div><div class="ttdeci">#define TIM_CR2_CCPC</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19408</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab0ee123675d8b8f98b5a6eeeccf37912"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912">TIM_CCMR1_IC1F</a></div><div class="ttdeci">#define TIM_CCMR1_IC1F</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19693</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab1cf04e70ccf3d4aba5afcf2496a411a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab1cf04e70ccf3d4aba5afcf2496a411a">TIM_BDTR_OSSI</a></div><div class="ttdeci">#define TIM_BDTR_OSSI</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19934</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab3c8126b8cc13f3338b59f1e91202d43"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab3c8126b8cc13f3338b59f1e91202d43">TIM_BDTR_BK2BID</a></div><div class="ttdeci">#define TIM_BDTR_BK2BID</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19975</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab46b7186665f5308cd2ca52acfb63e72"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72">TIM_CCMR1_IC1PSC</a></div><div class="ttdeci">#define TIM_CCMR1_IC1PSC</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19687</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab9c5878e85ce02c22d8a374deebd1b6e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e">TIM_CCMR1_OC1FE</a></div><div class="ttdeci">#define TIM_CCMR1_OC1FE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19641</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab9e197a78484567d4c6093c28265f3eb"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab9e197a78484567d4c6093c28265f3eb">TIM_DCR_DBL</a></div><div class="ttdeci">#define TIM_DCR_DBL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19989</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab9f47792b1c2f123464a2955f445c811"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811">TIM_DIER_UDE</a></div><div class="ttdeci">#define TIM_DIER_UDE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19532</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gabcf985e9c78f15e1e44b2bc4d2bafc67"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gabcf985e9c78f15e1e44b2bc4d2bafc67">TIM_BDTR_DTG</a></div><div class="ttdeci">#define TIM_BDTR_DTG</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19916</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gabf9051ecac123cd89f9d2a835e4cde2e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gabf9051ecac123cd89f9d2a835e4cde2e">TIM_DCR_DBA</a></div><div class="ttdeci">#define TIM_DCR_DBA</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19980</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gac8c03fabc10654d2a3f76ea40fcdbde6"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6">TIM_SR_UIF</a></div><div class="ttdeci">#define TIM_SR_UIF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19555</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gacacc4ff7e5b75fd2e4e6b672ccd33a72"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72">TIM_CR1_CKD</a></div><div class="ttdeci">#define TIM_CR1_CKD</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19397</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gacade8a06303bf216bfb03140c7e16cac"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac">TIM_SR_CC4IF</a></div><div class="ttdeci">#define TIM_SR_CC4IF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19567</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gacb338853d60dffd23d45fc67b6649705"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gacb338853d60dffd23d45fc67b6649705">TIM_BDTR_BK2F</a></div><div class="ttdeci">#define TIM_BDTR_BK2F</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19956</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gacea10770904af189f3aaeb97b45722aa"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa">TIM_CR1_DIR</a></div><div class="ttdeci">#define TIM_CR1_DIR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19383</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad07504497b70af628fa1aee8fe7ef63c"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c">TIM_CR2_TI1S</a></div><div class="ttdeci">#define TIM_CR2_TI1S</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19425</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad16e2f81b0c4fe28e323f3302c2240db"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad16e2f81b0c4fe28e323f3302c2240db">TIM_SR_CC6IF</a></div><div class="ttdeci">#define TIM_SR_CC6IF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19597</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad3cf234a1059c0a04799e88382cdc0f2"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2">TIM_SR_CC3IF</a></div><div class="ttdeci">#define TIM_SR_CC3IF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19564</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadb06f8bb364307695c7d6a028391de7b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadb06f8bb364307695c7d6a028391de7b">TIM_EGR_COMG</a></div><div class="ttdeci">#define TIM_EGR_COMG</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19620</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadce130a8f74c02de0f6e2f8cb0f16b6e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadce130a8f74c02de0f6e2f8cb0f16b6e">TIM_CCR5_GC5C1</a></div><div class="ttdeci">#define TIM_CCR5_GC5C1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19900</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gade656832d3ec303a2a7a422638dd560e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e">TIM_CR2_CCDS</a></div><div class="ttdeci">#define TIM_CR2_CCDS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19414</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gade8a374e04740aac1ece248b868522fe"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe">TIM_DIER_COMIE</a></div><div class="ttdeci">#define TIM_DIER_COMIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19523</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae181bb16ec916aba8ba86f58f745fdfd"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd">TIM_DIER_CC1DE</a></div><div class="ttdeci">#define TIM_DIER_CC1DE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19535</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae199132077792fb8efa01b87edd1c033"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae199132077792fb8efa01b87edd1c033">TIM_CR2_MMS2</a></div><div class="ttdeci">#define TIM_CR2_MMS2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19456</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae2be17c432a12ce3ec4a79aa380a01b6"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae2be17c432a12ce3ec4a79aa380a01b6">TIM_BDTR_BKF</a></div><div class="ttdeci">#define TIM_BDTR_BKF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19953</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae2ed8b32d9eb8eea251bd1dac4f34668"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae2ed8b32d9eb8eea251bd1dac4f34668">TIM_SMCR_ETF</a></div><div class="ttdeci">#define TIM_SMCR_ETF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19486</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae6c84655ac31844ff644f796ef638e06"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae6c84655ac31844ff644f796ef638e06">TIM_SR_SBIF</a></div><div class="ttdeci">#define TIM_SR_SBIF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19600</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae92349731a6107e0f3a251b44a67c7ea"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea">TIM_SMCR_SMS</a></div><div class="ttdeci">#define TIM_SMCR_SMS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19465</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaef0c136d9338baf71a64ff650b385645"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaef0c136d9338baf71a64ff650b385645">TIM_SR_B2IF</a></div><div class="ttdeci">#define TIM_SR_B2IF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19579</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf0328c1339b2b1633ef7a8db4c02d0d5"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf0328c1339b2b1633ef7a8db4c02d0d5">TIM_CR2_CCUS</a></div><div class="ttdeci">#define TIM_CR2_CCUS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19411</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf0c8b29f2a8d1426cf31270643d811c7"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf0c8b29f2a8d1426cf31270643d811c7">TIM_CR1_UIFREMAP</a></div><div class="ttdeci">#define TIM_CR1_UIFREMAP</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19403</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf7a2d4c831eb641ba082156e41d03358"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358">TIM_SR_CC3OF</a></div><div class="ttdeci">#define TIM_SR_CC3OF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19588</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf9435f36d53c6be1107e57ab6a82c16e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf9435f36d53c6be1107e57ab6a82c16e">TIM_BDTR_OSSR</a></div><div class="ttdeci">#define TIM_BDTR_OSSR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:19937</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaff4d8ae0f229b42960fe34be62a3b499"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaff4d8ae0f229b42960fe34be62a3b499">TIM_TISEL_TI2SEL</a></div><div class="ttdeci">#define TIM_TISEL_TI2SEL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:20104</div></div>
<div class="ttc" id="astm32h7xx_8h_html"><div class="ttname"><a href="stm32h7xx_8h.html">stm32h7xx.h</a></div><div class="ttdoc">CMSIS STM32H7xx Device Peripheral Access Layer Header File.</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html"><div class="ttname"><a href="struct_t_i_m___type_def.html">TIM_TypeDef</a></div><div class="ttdoc">TIM.</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1525</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a04248d87f48303fd2267810104a7878d"><div class="ttname"><a href="struct_t_i_m___type_def.html#a04248d87f48303fd2267810104a7878d">TIM_TypeDef::EGR</a></div><div class="ttdeci">__IO uint32_t EGR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1531</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a0dd9c06729a5eb6179c6d0d60faca7ed"><div class="ttname"><a href="struct_t_i_m___type_def.html#a0dd9c06729a5eb6179c6d0d60faca7ed">TIM_TypeDef::CCR1</a></div><div class="ttdeci">__IO uint32_t CCR1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1539</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a0f2291e7efdf3222689ef13e9be2ea4a"><div class="ttname"><a href="struct_t_i_m___type_def.html#a0f2291e7efdf3222689ef13e9be2ea4a">TIM_TypeDef::CCMR1</a></div><div class="ttdeci">__IO uint32_t CCMR1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1532</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a137d3523b60951eca1e4130257b2b23d"><div class="ttname"><a href="struct_t_i_m___type_def.html#a137d3523b60951eca1e4130257b2b23d">TIM_TypeDef::BDTR</a></div><div class="ttdeci">__IO uint32_t BDTR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1543</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a22a33c78ca5bec0e3e8559164a82b8ef"><div class="ttname"><a href="struct_t_i_m___type_def.html#a22a33c78ca5bec0e3e8559164a82b8ef">TIM_TypeDef::DIER</a></div><div class="ttdeci">__IO uint32_t DIER</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1529</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a374f851b5f1097a3ebd3f494ded6512a"><div class="ttname"><a href="struct_t_i_m___type_def.html#a374f851b5f1097a3ebd3f494ded6512a">TIM_TypeDef::CCR6</a></div><div class="ttdeci">__IO uint32_t CCR6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1549</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a48ce9972eb643ae4f34bd75a0b931ad4"><div class="ttname"><a href="struct_t_i_m___type_def.html#a48ce9972eb643ae4f34bd75a0b931ad4">TIM_TypeDef::TISEL</a></div><div class="ttdeci">__IO uint32_t TISEL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1552</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a4d1171e9a61538424b8ef1f2571986d0"><div class="ttname"><a href="struct_t_i_m___type_def.html#a4d1171e9a61538424b8ef1f2571986d0">TIM_TypeDef::CCR2</a></div><div class="ttdeci">__IO uint32_t CCR2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1540</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a5ba381c3f312fdf5e0b4119641b3b0aa"><div class="ttname"><a href="struct_t_i_m___type_def.html#a5ba381c3f312fdf5e0b4119641b3b0aa">TIM_TypeDef::CCR4</a></div><div class="ttdeci">__IO uint32_t CCR4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1542</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a67d30593bcb68b98186ebe5bc8dc34b1"><div class="ttname"><a href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">TIM_TypeDef::SMCR</a></div><div class="ttdeci">__IO uint32_t SMCR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1528</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a6a42766a6ca3c7fe10a810ebd6b9d627"><div class="ttname"><a href="struct_t_i_m___type_def.html#a6a42766a6ca3c7fe10a810ebd6b9d627">TIM_TypeDef::ARR</a></div><div class="ttdeci">__IO uint32_t ARR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1537</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a6b1ae85138ed91686bf63699c61ef835"><div class="ttname"><a href="struct_t_i_m___type_def.html#a6b1ae85138ed91686bf63699c61ef835">TIM_TypeDef::CR2</a></div><div class="ttdeci">__IO uint32_t CR2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1527</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a6fdd2a7fb88d28670b472aaac0d9d262"><div class="ttname"><a href="struct_t_i_m___type_def.html#a6fdd2a7fb88d28670b472aaac0d9d262">TIM_TypeDef::CNT</a></div><div class="ttdeci">__IO uint32_t CNT</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1535</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a7a81e7aac9bef80b126097f8e9f36d07"><div class="ttname"><a href="struct_t_i_m___type_def.html#a7a81e7aac9bef80b126097f8e9f36d07">TIM_TypeDef::AF1</a></div><div class="ttdeci">__IO uint32_t AF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1550</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a7efe9ea8067044cac449ada756ebc2d1"><div class="ttname"><a href="struct_t_i_m___type_def.html#a7efe9ea8067044cac449ada756ebc2d1">TIM_TypeDef::DCR</a></div><div class="ttdeci">__IO uint32_t DCR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1544</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_a9dafc8b03e8497203a8bb395db865328"><div class="ttname"><a href="struct_t_i_m___type_def.html#a9dafc8b03e8497203a8bb395db865328">TIM_TypeDef::CR1</a></div><div class="ttdeci">__IO uint32_t CR1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1526</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_ac83441bfb8d0287080dcbd945a272a74"><div class="ttname"><a href="struct_t_i_m___type_def.html#ac83441bfb8d0287080dcbd945a272a74">TIM_TypeDef::CCR3</a></div><div class="ttdeci">__IO uint32_t CCR3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1541</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_acedfc978c879835c05ef1788ad26b2ff"><div class="ttname"><a href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">TIM_TypeDef::SR</a></div><div class="ttdeci">__IO uint32_t SR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1530</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_ad03c852f58077a11e75f8af42fa6d921"><div class="ttname"><a href="struct_t_i_m___type_def.html#ad03c852f58077a11e75f8af42fa6d921">TIM_TypeDef::PSC</a></div><div class="ttdeci">__IO uint32_t PSC</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1536</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_ad432e2a315abf68e6c295fb4ebc37534"><div class="ttname"><a href="struct_t_i_m___type_def.html#ad432e2a315abf68e6c295fb4ebc37534">TIM_TypeDef::RCR</a></div><div class="ttdeci">__IO uint32_t RCR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1538</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_ad7271cc1eec9ef16e4ee5401626c0b3b"><div class="ttname"><a href="struct_t_i_m___type_def.html#ad7271cc1eec9ef16e4ee5401626c0b3b">TIM_TypeDef::CCER</a></div><div class="ttdeci">__IO uint32_t CCER</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1534</div></div>
<div class="ttc" id="astruct_t_i_m___type_def_html_af30dc563e6c1b7b7e01e393feb484080"><div class="ttname"><a href="struct_t_i_m___type_def.html#af30dc563e6c1b7b7e01e393feb484080">TIM_TypeDef::CCR5</a></div><div class="ttdeci">__IO uint32_t CCR5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:1548</div></div>
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